From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 22181 invoked by alias); 29 Jun 2009 19:45:00 -0000 Received: (qmail 22076 invoked by uid 48); 29 Jun 2009 19:44:45 -0000 Date: Mon, 29 Jun 2009 19:45:00 -0000 Message-ID: <20090629194445.22075.qmail@sourceware.org> X-Bugzilla-Reason: CC References: Subject: [Bug target/37488] register allocation spills floats needlessly In-Reply-To: Reply-To: gcc-bugzilla@gcc.gnu.org To: gcc-bugs@gcc.gnu.org From: "vmakarov at redhat dot com" Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org X-SW-Source: 2009-06/txt/msg02135.txt.bz2 ------- Comment #7 from vmakarov at redhat dot com 2009-06-29 19:44 ------- Paolo, Steven, thanks for looking into this problem. Using the mips approach is a good idea. Although the costs of FLOAT_REGS and SSE_REGS are the same in ira-costs.c, IRA should prefer SSE_REGS or FLOAT_REGS depending on -fpmath= option. The implementation will take some time because choosing a cover class depends not only on order of them in IRA_COVER_CLASSES macro but also on order of them in enum reg_class. I hope I'll have a patch on this week. -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=37488