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From: "lessen42+gcc at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug middle-end/40893] ARM and PPC truncate intermediate operations unnecessarily
Date: Tue, 28 Jul 2009 22:28:00 -0000	[thread overview]
Message-ID: <20090728222740.25108.qmail@sourceware.org> (raw)
In-Reply-To: <bug-40893-17992@http.gcc.gnu.org/bugzilla/>



------- Comment #1 from lessen42+gcc at gmail dot com  2009-07-28 22:27 -------
More specifically, on x86_64 the following is generated with gcc-4.4 -O3
-march=core2 -S
_dct2x2dc_dconly:
        movswl  2(%rdi),%edx
        pushq   %rbp
        addw    (%rdi), %dx
        movswl  6(%rdi),%eax
        movq    %rsp, %rbp
        addw    4(%rdi), %ax
        leal    (%rax,%rdx), %ecx
        subw    %ax, %dx
        movw    %cx, (%rdi)
        movw    %dx, 2(%rdi)
        leave
        ret

So it seems that the optimizer realizes that you don't need registers larger
than 16-bits, which allows memory operands on x86, which is optimal for this
case. However, other architectures follow this too literally, wasting
instructions to truncate intermediate results to 16 bits.


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=40893


  reply	other threads:[~2009-07-28 22:28 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-07-28 16:28 [Bug middle-end/40893] New: " lessen42+gcc at gmail dot com
2009-07-28 22:28 ` lessen42+gcc at gmail dot com [this message]
2009-09-09 16:34 ` [Bug middle-end/40893] " ramana at gcc dot gnu dot org
     [not found] <bug-40893-4@http.gcc.gnu.org/bugzilla/>
2010-10-05 18:14 ` paul at pwsan dot com
2010-10-08 13:05 ` rearnsha at gcc dot gnu.org
2010-10-08 17:17 ` paul at pwsan dot com

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