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From: "pinskia at gcc dot gnu dot org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug middle-end/40615] unnecessary CSE
Date: Tue, 29 Sep 2009 05:50:00 -0000 [thread overview]
Message-ID: <20090929055006.937.qmail@sourceware.org> (raw)
In-Reply-To: <bug-40615-17659@http.gcc.gnu.org/bugzilla/>
------- Comment #5 from pinskia at gcc dot gnu dot org 2009-09-29 05:50 -------
PowerPC has the same issue. Instructions on PPC are all the same size so 3
adds are better than one add plus 3 register moves.
Here is a C example:
int f(int *a);
int g(int *a);
int h(int *a);
void hh(void)
{
int t;
f(&t);
g(&t);
h(&t);
}
--- CUT ---
Most RISC will have the same issue as most will have instructions which are
fixed length.
I bet this has to do with hard registers.
--
pinskia at gcc dot gnu dot org changed:
What |Removed |Added
----------------------------------------------------------------------------
Component|target |middle-end
GCC build triplet|i686-linux |
GCC target triplet|arm-eabi |arm-eabi, powerpc*-*-*
Keywords| |missed-optimization
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=40615
next prev parent reply other threads:[~2009-09-29 5:50 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-07-02 7:39 [Bug target/40615] New: " carrot at google dot com
2009-07-02 7:39 ` [Bug target/40615] " carrot at google dot com
2009-07-02 8:53 ` ramana at gcc dot gnu dot org
2009-07-02 9:16 ` steven at gcc dot gnu dot org
2009-07-02 9:39 ` ramana at gcc dot gnu dot org
2009-09-29 5:50 ` pinskia at gcc dot gnu dot org [this message]
2009-09-29 5:51 ` [Bug rtl-optimization/40615] " pinskia at gcc dot gnu dot org
2010-03-20 19:30 ` ramana at gcc dot gnu dot org
2010-06-04 12:44 ` bernds at gcc dot gnu dot org
2010-06-07 22:50 ` bernds at gcc dot gnu dot org
2010-06-08 15:31 ` hjl dot tools at gmail dot com
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