[Bug target/42536] New: [4.4/4.5 regression] ICE in spill_failure, at reload1.c:2141

[Bug target/42536] New: [4.4/4.5 regression] ICE in spill_failure, at reload1.c:2141

[debian-gcc at lists dot debian dot org]

seen with 20091228 trunk and 4.4 branch on i486-linux-gnu, not seen with 4.3
branch (opening new report, because PR39431 is fixed for 4.4 and 4.5). Adding
-fomit-frame-pointer avoids the ice.

  Matthias

$ /usr/lib/gcc-snapshot/bin/gcc -g -O2 -fno-gcse -fno-inline-functions
-fno-unit-at-a-time -fstack-protector -c cvm.i 
cvm.c: In function '_ILCVMInterpreter':
cvm.c:889:1: error: unable to find a register to spill in class 'GENERAL_REGS'
cvm.c:889:1: error: this is the insn:
(insn 11992 11991 11993 863 cvm_ptr.c:66 (set (mem:DI (plus:SI (plus:SI
(mult:SI (reg:SI 6750 [ D.20325 ])
                        (const_int 8 [0x8]))
                    (reg/f:SI 6746 [ tempptr.3460 ]))
                (const_int 4 [0x4])) [16 S8 A64])
        (reg:DI 12123)) 88 {*movdi_2} (expr_list:REG_DEAD (reg:DI 12123)
        (expr_list:REG_DEAD (reg:SI 6750 [ D.20325 ])
            (expr_list:REG_DEAD (reg/f:SI 6746 [ tempptr.3460 ])
                (nil)))))
cvm.c:889:1: internal compiler error: in spill_failure, at reload1.c:2141
Please submit a full bug report,
with preprocessed source if appropriate.


-- 
           Summary: [4.4/4.5 regression] ICE in spill_failure, at
                    reload1.c:2141
           Product: gcc
           Version: 4.5.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
        AssignedTo: unassigned at gcc dot gnu dot org
        ReportedBy: debian-gcc at lists dot debian dot org


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42536

[Bug target/42536] [4.4/4.5 regression] ICE in spill_failure, at reload1.c:2141

[debian-gcc at lists dot debian dot org]

------- Comment #1 from debian-gcc at lists dot debian dot org  2009-12-29 12:41 -------
Created an attachment (id=19411)
 --> (http://gcc.gnu.org/bugzilla/attachment.cgi?id=19411&action=view)
preprocessed source


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42536

[Bug target/42536] [4.4/4.5 regression] ICE in spill_failure, at reload1.c:2141

[rguenth at gcc dot gnu dot org]

-- 

rguenth at gcc dot gnu dot org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |ra
   Target Milestone|---                         |4.4.3


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42536

[Bug target/42536] [4.4/4.5 regression] ICE in spill_failure, at reload1.c:2141

[jakub at gcc dot gnu dot org]

------- Comment #2 from jakub at gcc dot gnu dot org  2010-01-02 14:30 -------
With 3 register vars in the function (ebx, edi, esi) on the register starved
ix86 the error is tollerable.  From the 8 registers the programmer takes 3,
%esp is fixed, without -fomit-frame-pointer %ebp is fixed too, which leaves
just %eax, %edx and %ecx for register allocation.  Even if this happens to
compile, the result can't work fast, as almost all insns need to have
temporaries spilled and reread back.


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42536

[Bug target/42536] [4.4/4.5 regression] ICE in spill_failure, at reload1.c:2141

[jakub at gcc dot gnu dot org]

------- Comment #3 from jakub at gcc dot gnu dot org  2010-01-02 16:44 -------
Reduced testcase:
/* { dg-do compile { target { { i?86-*-* x86_64-*-* } && ilp32 } } } */
/* { dg-options "-O2 -fno-gcse" } */

struct C;
struct B { struct C *b; };
struct C { void (*baz) (struct B *, void *, int); };
typedef union { int f; void *e; } D;
struct E { struct B *e; };
struct A { struct E *a1; D *a2; D *a3; };

void
foo (long *x, long y)
{
  *(long long *) x = y;
}

extern long fn1 (D);
extern void fn2 (void);

void
_bar (struct A *x)
{
  register int a asm ("esi");
  register D *volatile b asm ("edi");
  register int c asm ("ebx");
  void *d;
  asm volatile ("" : "=r" (a), "=r" (b), "=r" (c) : : "memory");
  if ((d = b[-2].e) != 0 && b [-2].e < d)
    {
      foo (&(((long *) d) + 1) [b[0].f], fn1 (b[-1]));
      x->a2 = (D *) c;
      x->a3 = b;
      fn2 ();
    }
  x->a1->e->b->baz (x->a1->e, (void *) (long) a, 1);
}

Wonder why RA doesn't try to force the memory address into register, that would
free up one register from the 4 otherwise needed (2 for the address, 2 for
DImode value being stored into the memory). 


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42536

[Bug target/42536] [4.4/4.5 regression] ICE in spill_failure, at reload1.c:2141

[rguenth at gcc dot gnu dot org]

-- 

rguenth at gcc dot gnu dot org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Priority|P3                          |P2


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42536

[Bug target/42536] [4.4/4.5 regression] ICE in spill_failure, at reload1.c:2141

[jakub at gcc dot gnu dot org]

-- 

jakub at gcc dot gnu dot org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|4.4.3                       |4.4.4


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42536

[Bug target/42536] [4.4/4.5 regression] ICE in spill_failure, at reload1.c:2141

[steven at gcc dot gnu dot org]

-- 

steven at gcc dot gnu dot org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
     Ever Confirmed|0                           |1
   Last reconfirmed|0000-00-00 00:00:00         |2010-03-20 13:03:43
               date|                            |


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42536

[Bug target/42536] [4.4/4.5/4.6 regression] ICE in spill_failure, at reload1.c:2141

[jakub at gcc dot gnu dot org]

-- 

jakub at gcc dot gnu dot org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|4.4.4                       |4.4.5


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42536

[Bug target/42536] [4.4/4.5/4.6 regression] ICE in spill_failure, at reload1.c:2141

[vmakarov at redhat dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42536

Vladimir Makarov <vmakarov at redhat dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |vmakarov at redhat dot com

--- Comment #6 from Vladimir Makarov <vmakarov at redhat dot com> 2010-11-29 20:39:39 UTC ---
(In reply to comment #4)
> Jeff/Vlad, how hard would it be to try to split the insn into two insns instead
> of a spill failure (for insns using a MEM whose address uses more than one hard
> register) - one which forces the address into register (assuming it is
> supported) and the store (or load) which would use a simpler address form?

If it is done in reload (and imho this is the most right place to do), I think
it would be hard.  It needs some person with a good knowledge of the reload.

It is also possible to do some splitting in other parts of compiler but it
would an approximate solution (it means not all such cases will be avoided
or/and it will hurt performance in general case).

[Bug target/42536] [4.4/4.5/4.6 regression] ICE in spill_failure, at reload1.c:2141

[law at redhat dot com]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42536

Jeffrey A. Law <law at redhat dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |law at redhat dot com

--- Comment #5 from Jeffrey A. Law <law at redhat dot com> 2010-11-29 20:33:14 UTC ---
I guess it would be possible for reload to split an insn in some circumstances,
particularly when there's complex addressing modes and multiple registers dying
within the insn.

As you know, I've been poking at range splitting and we might be able to model
this case too.  Right now I split based on unallocated pseudos and expect to
split ranges based on pseudos getting the wrong kind of register in the future.

However, there's a couple areas were we still want to split ranges and we may
be able to come up with a generic way to express the other ranges we want to
split:

[Bug target/42536] [4.4/4.5/4.6 regression] ICE in spill_failure, at reload1.c:2141

[jakub at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42536

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |jakub at gcc dot gnu.org,
                   |                            |law at gcc dot gnu.org,
                   |                            |vmakarov at gcc dot gnu.org
      Known to fail|                            |

--- Comment #4 from Jakub Jelinek <jakub at gcc dot gnu.org> 2010-11-29 19:50:18 UTC ---
Jeff/Vlad, how hard would it be to try to split the insn into two insns instead
of a spill failure (for insns using a MEM whose address uses more than one hard
register) - one which forces the address into register (assuming it is
supported) and the store (or load) which would use a simpler address form?

[Bug target/42536] [4.4/4.5/4.6 regression] ICE in spill_failure, at reload1.c:2141

[jakub at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42536

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|4.4.5                       |4.4.6