[Bug target/42172] New: inefficient bit fields assignments

[Bug target/42172] New: inefficient bit fields assignments

[carrot at google dot com]

The attached test case contains several continuous bit fields assignment,
compile it with options -mthumb -Os, gcc generates

        .fnstart
.LFB1:
        ldrb    r3, [r0]
        mov     r2, #7
        bic     r3, r3, r2
        strb    r3, [r0]
        ldrb    r3, [r0]
        mov     r2, #56
        bic     r3, r3, r2
        mov     r2, #8
        orr     r3, r3, r2
        strb    r3, [r0]
        ldrb    r3, [r0]
        mov     r2, #64
        bic     r3, r3, r2
        strb    r3, [r0]
        ldrb    r2, [r0]
        mov     r3, #127
        and     r3, r3, r2
        strb    r3, [r0]
        @ sp needed for prologue
        bx      lr

The 4 fields are contained in one word, for each field assignment the code
loads the word, changes the field, then write the word back. A better code
sequence should load the word once, change all 4 fields, then write back the
changed word.

        ldrb    r3, [r0]
        mov     r2, #255             // bit mask
        bic     r3, r3, r2
        mov     r2, #8               // the new value of all 4 fields
        orr     r3, r3, r2
        strb    r3, [r0]
        @ sp needed for prologue
        bx      lr

or more aggressively if the word contains only these four fields

        mov     r3, #8
        strb    r3, [r0]
        @ sp needed for prologue
        bx      lr


-- 
           Summary: inefficient bit fields assignments
           Product: gcc
           Version: 4.5.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
        AssignedTo: unassigned at gcc dot gnu dot org
        ReportedBy: carrot at google dot com
 GCC build triplet: i686-linux
  GCC host triplet: i686-linux
GCC target triplet: arm-eabi


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

[Bug target/42172] inefficient bit fields assignments

[carrot at google dot com]

------- Comment #1 from carrot at google dot com  2009-11-25 09:16 -------
Created an attachment (id=19147)
 --> (http://gcc.gnu.org/bugzilla/attachment.cgi?id=19147&action=view)
test case


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

[Bug target/42172] inefficient bit fields assignments

[jakub at gcc dot gnu dot org]

------- Comment #2 from jakub at gcc dot gnu dot org  2009-11-25 09:40 -------


*** This bug has been marked as a duplicate of 37135 ***


-- 

jakub at gcc dot gnu dot org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|                            |DUPLICATE


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

[Bug target/42172] inefficient bit fields assignments

[bernds at gcc dot gnu dot org]

------- Comment #3 from bernds at gcc dot gnu dot org  2010-07-02 16:26 -------
Subject: Bug 42172

Author: bernds
Date: Fri Jul  2 16:25:59 2010
New Revision: 161726

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=161726
Log:
        PR target/42172
        * config/arm/arm.c (thumb1_rtx_costs): Improve support for SIGN_EXTEND
        and ZERO_EXTEND.
        (arm_rtx_costs_1): Likewise.
        (arm_size_rtx_costs): Use arm_rtx_costs_1 for these codes.
        * config/arm/arm.md (is_arch6): New attribute.
        (zero_extendhisi2, zero_extendqisi2, extendhisi2,
        extendqisi2): Tighten the code somewhat, avoiding invalid
        RTL to occur in the expander patterns.
        (thumb1_zero_extendhisi2): Merge with thumb1_zero_extendhisi2_v6.
        (thumb1_zero_extendhisi2_v6): Delete.
        (thumb1_extendhisi2): Merge with thumb1_extendhisi2_v6.
        (thumb1_extendhisi2_v6): Delete.
        (thumb1_extendqisi2): Merge with thumb1_extendhisi2_v6.
        (thumb1_extendqisi2_v6): Delete.
        (zero_extendhisi2 for register input splitter): New.
        (zero_extendqisi2 for register input splitter): New.
        (thumb1_extendhisi2 for register input splitter): New.
        (extendhisi2 for register input splitter): New.
        (extendqisi2 for register input splitter): New.
        (TARGET_THUMB1 extendqisi2 for memory input splitter): New.
        (arm_zero_extendhisi2): Allow nonimmediate_operand for operand 1,
        and add support for a register alternative requiring a split.
        (thumb1_zero_extendqisi2): Likewise.
        (arm_zero_extendqisi2): Likewise.
        (arm_extendhisi2): Likewise.
        (arm_extendqisi2): Likewise.

testsuite/
        PR target/42172
        * gcc.target/arm/pr42172-1.c: New test.


Added:
    trunk/gcc/testsuite/gcc.target/arm/pr42172-1.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/arm/arm.c
    trunk/gcc/config/arm/arm.md
    trunk/gcc/testsuite/ChangeLog


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

[Bug tree-optimization/42172] inefficient bit fields assignments

[bernds at gcc dot gnu dot org]

------- Comment #4 from bernds at gcc dot gnu dot org  2010-08-09 15:04 -------
I'm reopening this as it's not fixed, and even if we fix it in the RTL
optimizers, it should stay open as a reminder that we produce poor initial RTL.


-- 

bernds at gcc dot gnu dot org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|RESOLVED                    |UNCONFIRMED
          Component|target                      |tree-optimization
         Resolution|DUPLICATE                   |


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

[Bug tree-optimization/42172] inefficient bit fields assignments

[bernds at gcc dot gnu dot org]

------- Comment #5 from bernds at gcc dot gnu dot org  2010-08-19 17:32 -------
Subject: Bug 42172

Author: bernds
Date: Thu Aug 19 17:31:57 2010
New Revision: 163383

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=163383
Log:
        PR target/42172
        * combine.c (combine_validate_cost): New arg I0.  All callers changed.
        Take its cost into account if nonnull.
        (insn_a_feeds_b): New static function.
        (combine_instructions): Look for four-insn combinations.
        (can_combine_p): New args PRED2, SUCC2.  All callers changed.  Take
        them into account when computing all_adjacent and looking for other
        uses.
        (combinable_i3pat): New args I0DEST, I0_NOT_IN_SRC.  All callers
        changed.  Treat them like I1DEST and I1_NOT_IN_SRC.
        (try_combine): New arg I0.  Handle four-insn combinations.
        (distribute_notes): New arg ELIM_I0.  All callers changed.  Treat it
        like ELIM_I1.

Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/combine.c


-- 


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

[Bug tree-optimization/42172] inefficient bit fields assignments

[ramana at gcc dot gnu dot org]

------- Comment #6 from ramana at gcc dot gnu dot org  2010-09-01 09:07 -------
Leaving this open as per comment #4


-- 

ramana at gcc dot gnu dot org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
     Ever Confirmed|0                           |1
   Last reconfirmed|0000-00-00 00:00:00         |2010-09-01 09:07:00
               date|                            |


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

[Bug tree-optimization/42172] inefficient bit fields assignments

[ramana at gcc dot gnu dot org]

-- 

ramana at gcc dot gnu dot org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |4.6.0


http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

[Bug tree-optimization/42172] inefficient bit fields assignments

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
   Target Milestone|---                         |7.0
             Status|NEW                         |RESOLVED

--- Comment #12 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Fixed already fully in GCC 7, there are already testcases committed for this.
Most likely r7-4171 .

[Bug tree-optimization/42172] inefficient bit fields assignments

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |missed-optimization
           Severity|normal                      |enhancement

[Bug tree-optimization/42172] inefficient bit fields assignments

[segher at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

Segher Boessenkool <segher at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |segher at gcc dot gnu.org

--- Comment #11 from Segher Boessenkool <segher at gcc dot gnu.org> ---
I have code to improve zero_extract (and similar) handling in
combine.  For stage1, obviously.

[Bug tree-optimization/42172] inefficient bit fields assignments

[amker at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

amker at gcc dot gnu.org changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |amker at gcc dot gnu.org

--- Comment #9 from amker at gcc dot gnu.org ---
Created attachment 35265
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=35265&action=edit
rtl dump for both cortex-m0 and cortex-m3

[Bug tree-optimization/42172] inefficient bit fields assignments

[janis at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

Janis Johnson <janis at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |janis at gcc dot gnu.org

--- Comment #8 from Janis Johnson <janis at gcc dot gnu.org> 2013-01-17 00:26:10 UTC ---
The test gcc.target/arm/pr42172-1.c currently passes for armv6t2, armv7*, and
armv8* with and without -mthumb.  At this point can the test be limited to
those processors, or XFAILed for others?

[Bug tree-optimization/42172] inefficient bit fields assignments

[rguenth at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

Richard Guenther <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|4.6.1                       |---

[Bug tree-optimization/42172] inefficient bit fields assignments

[jakub at gcc dot gnu.org]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=42172

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|4.6.0                       |4.6.1

--- Comment #7 from Jakub Jelinek <jakub at gcc dot gnu.org> 2011-03-25 19:53:14 UTC ---
GCC 4.6.0 is being released, adjusting target milestone.