From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 24455 invoked by alias); 8 Sep 2010 17:44:48 -0000 Received: (qmail 24400 invoked by uid 48); 8 Sep 2010 17:44:34 -0000 Date: Wed, 08 Sep 2010 17:44:00 -0000 Message-ID: <20100908174434.24399.qmail@sourceware.org> X-Bugzilla-Reason: CC References: Subject: [Bug middle-end/40386] wrong code generation for several SPEC CPU2000 benchmarks (lucas, mgrid, face, applu, apsi) with -O1 -fno-ira-share-spill-slots In-Reply-To: Reply-To: gcc-bugzilla@gcc.gnu.org To: gcc-bugs@gcc.gnu.org From: "vmakarov at redhat dot com" Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org X-SW-Source: 2010-09/txt/msg01078.txt.bz2 ------- Comment #9 from vmakarov at redhat dot com 2010-09-08 17:44 ------- The problem is in that pseudos (r121 in our case) spilled by IRA are not added to live_throughout of reload chain. As the result, pseudo_forbidden_regs are not set up for such pseudos and they can get a hard registers (42 in our case) even if they live through insns (insn 153 in our case) using reload (0th in our case) with this register when another pseudo is spilled and reload ask IRA to assign the correspodning hard register to other pseudo. Here are some parts of IRA dump: Spilling for insn 153. Using reg 2 for reload 1 Using reg 42 for reload 0 ... Spilling for insn 238. Using reg 2 for reload 0 Spill 117(a35), cost=5000 Spilled regs 117 Try assign 121(a6), cost=5000: reassign to 42 The fix is pretty simple. I'll send it soon. -- http://gcc.gnu.org/bugzilla/show_bug.cgi?id=40386