From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 32469 invoked by alias); 27 Oct 2010 18:00:24 -0000 Received: (qmail 32424 invoked by uid 22791); 27 Oct 2010 18:00:22 -0000 X-SWARE-Spam-Status: No, hits=-2.3 required=5.0 tests=ALL_TRUSTED,AWL,BAYES_00,MISSING_MID,TW_ZJ X-Spam-Check-By: sourceware.org Received: from localhost (HELO gcc.gnu.org) (127.0.0.1) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 27 Oct 2010 18:00:18 +0000 From: "ubizjak at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/46198] movd xmm, r (xmm -> GPR) may hit the stack X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: enhancement X-Bugzilla-Who: ubizjak at gmail dot com X-Bugzilla-Status: RESOLVED X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Changed-Fields: Status Resolution In-Reply-To: References: X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated Content-Type: text/plain; charset="UTF-8" MIME-Version: 1.0 Date: Wed, 27 Oct 2010 18:00:00 -0000 Mailing-List: contact gcc-bugs-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-bugs-owner@gcc.gnu.org X-SW-Source: 2010-10/txt/msg02319.txt.bz2 Message-ID: <20101027180000.TKKk4NF74K4gJKH8ysC_eN5Fmyd3YRRMi3nseJuSvnA@z> http://gcc.gnu.org/bugzilla/show_bug.cgi?id=46198 Uros Bizjak changed: What |Removed |Added ---------------------------------------------------------------------------- Status|UNCONFIRMED |RESOLVED Resolution| |INVALID --- Comment #1 from Uros Bizjak 2010-10-27 18:00:13 UTC --- This is all what TARGET_INTER_UNIT_MOVES is for. On AMD (and generic) targets, TARGET_INTER_UNIT_MOVES is disabled, for -march=core2 is enabled. The situation is thus totally under control ;) I recommend that you read [1], especially: Part 2: Optimizing subroutines in assembly language: An optimization guide for x86 platforms Part 3: The microarchitecture of Intel, AMD and VIA CPUs: An optimization guide for assembly programmers and compiler makers Part 4: Instruction tables: Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD and VIA CPUs [1] http://www.agner.org/optimize/