[Bug target/35363] Missing bit field coalescing optimization

["xinliangli at gmail dot com" <gcc-bugzilla@gcc.gnu.org>]

http://gcc.gnu.org/bugzilla/show_bug.cgi?id=35363

davidxl <xinliangli at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |xinliangli at gmail dot com
            Version|4.3.0                       |4.6.0

--- Comment #7 from davidxl <xinliangli at gmail dot com> 2010-11-03 00:20:46 UTC ---
(In reply to comment #6)
> The IL after MEM_REF lowering looks like
> 
> bar ()
> {
>   int D.1193;
>   unsigned int D.1192;
>   unsigned int D.1191;
>   unsigned int D.1190;
>   int D.1189;
> 
>   D.1189 = MEM <int {0}, &a>;
>   D.1190 = (unsigned int) D.1189;
>   D.1191 = D.1190 & 192;
>   D.1192 = D.1191 | 1048602;
>   D.1193 = (int) D.1192;
>   MEM <int {0}, &a> = D.1193;
>   return;
> }
> 
> foo ()
> {
>   int MEML.2;
>   int MEML.1;
>   int MEML.0;
> 
>   MEML.0 = MEM <int {0}, &a>;
>   MEML.0 = BIT_FIELD_EXPR <MEML.0, 2, 3, 0>;
>   MEM <int {0}, &a> = MEML.0;
>   MEML.1 = MEM <int {0}, &a>;
>   MEML.1 = BIT_FIELD_EXPR <MEML.1, 3, 3, 3>;
>   MEM <int {0}, &a> = MEML.1;
>   MEML.2 = MEM <int {0}, &a>;
>   MEML.2 = BIT_FIELD_EXPR <MEML.2, 8, 17, 8>;
>   MEM <int {0}, &a> = MEML.2;
>   return;
> }


LLVM generates expected code:

.Ltmp1:
    movl    $-33554240, %eax
    andl    a(%rip), %eax
    orl    $2074, %eax
    movl    %eax, a(%rip)

open64 is also bad.