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Subject: [Bug target/100028] [9/10/11 Regression] arm64 failure to generate
 bfxil
Date: Tue, 13 Apr 2021 10:44:20 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D100028

--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:f6ba5d039f988babdd99b5cdfb4557c380e57d69

commit r11-8149-gf6ba5d039f988babdd99b5cdfb4557c380e57d69
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Apr 13 12:43:39 2021 +0200

    aarch64: Restore bfxil optimization [PR100028]

    Similarly to PR87763 for bfi, the GCC 9 combiner changes to not combine
    moves from hard registers regressed the following testcase where we no
    longer recognize bfxil and emit 3 instructions instead.

    The following patch adds define_insn patterns that match what the combi=
ner
    is trying to match in these cases.  I haven't been able to see patterns
    with the other order of the IOR operands, seems the IL is canonicalized
this
    way no matter what is written in the source.

    2021-04-13  Jakub Jelinek  <jakub@redhat.com>

            PR target/100028
            * config/aarch64/aarch64.md (*aarch64_bfxil<mode>_extr,
            *aarch64_bfxilsi_extrdi): New define_insn patterns.

            * gcc.target/aarch64/pr100028.c: New test.=