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From: "jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/100028] [9/10/11 Regression] arm64 failure to generate
 bfxil
Date: Mon, 12 Apr 2021 14:08:53 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D100028

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|unassigned at gcc dot gnu.org      |jakub at gcc dot gn=
u.org
             Status|NEW                         |ASSIGNED

--- Comment #3 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
I guess it is basically a dup of PR87763, except that it needs yet another
pattern.
Combiner tries to match here:
    (ior:SI (and:SI (reg:SI 102)
            (const_int -8 [0xfffffffffffffff8]))
        (subreg:SI (zero_extract:DI (subreg:DI (reg:SI 103) 0)
                (const_int 3 [0x3])
                (const_int 11 [0xb])) 0)))
which is similar to:
(define_insn "*aarch64_bfi<GPI:mode>4_noand"
  [(set (match_operand:GPI 0 "register_operand" "=3Dr")
        (ior:GPI (and:GPI (match_operand:GPI 1 "register_operand" "0")
                          (match_operand:GPI 2 "const_int_operand" "n"))
                 (ashift:GPI
                          (match_operand:GPI 3 "register_operand" "r")
                          (match_operand:GPI 4 "aarch64_simd_shift_imm_<mod=
e>"
n"))))]
  "aarch64_masks_and_shift_for_bfi_p (<MODE>mode, UINTVAL (operands[2]),
                                     UINTVAL (operands[4]),
                                     HOST_WIDE_INT_M1U << UINTVAL (operands=
[4])
)"=