From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 36D773953CEC; Mon, 19 Apr 2021 17:00:19 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 36D773953CEC From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/100067] Unexpected warning for -mcpu=neoverse-n1 when configured with --with-fpu Date: Mon, 19 Apr 2021 17:00:19 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 11.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: rearnsha at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Apr 2021 17:00:19 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D100067 --- Comment #7 from CVS Commits --- The master branch has been updated by Richard Earnshaw : https://gcc.gnu.org/g:3bffc4b37e85c7f6092dfb0fbe4067d268e97b46 commit r11-8245-g3bffc4b37e85c7f6092dfb0fbe4067d268e97b46 Author: Richard Earnshaw Date: Mon Apr 19 16:56:31 2021 +0100 arm: partial revert of r11-8168 [PR100067] This is a partial revert of r11-8168. The overall purpose of the commit is retained (to fix a bogus warning when -mfpu=3D is used in combination with eg -mcpu=3Dneoverse-v1), but it removes the hunk that changed the subsequent feature bits for features of a simd/fp unit that cannot be described by -mfpu. While I still think that is the correct direction of travel, it's somewhat disruptive and not appropriate for late stage4. I'll revisit for gcc-12. gcc: PR target/100067 * config/arm/arm.c (arm_configure_build_target): Do not strip extended FPU/SIMD feature bits from the target ISA when -mfpu is specified (partial revert of r11-8168).=