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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/100075] [9/10/11 Regression] unneeded sign extension
Date: Fri, 16 Apr 2021 11:45:07 +0000	[thread overview]
Message-ID: <bug-100075-4-ajfydylC65@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-100075-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100075

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:47f42744f6e10ad41db926d739306e6f237fd3ac

commit r11-8215-g47f42744f6e10ad41db926d739306e6f237fd3ac
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Fri Apr 16 13:44:23 2021 +0200

    aarch64: Fix up 2 other combine opt regressions vs. GCC8 [PR100075]

    The testcase used to be compiled at -O2 by GCC8 and earlier to:
    f1:
            neg     w1, w0, asr 16
            and     w1, w1, 65535
            orr     w0, w1, w0, lsl 16
            ret
    f2:
            neg     w1, w0
            extr    w0, w1, w0, 16
            ret
    but since GCC9 (r9-3594 for f1 and r9-6926 for f2) we compile it into:
    f1:
            mov     w1, w0
            sbfx    x0, x1, 16, 16
            neg     w0, w0
            bfi     w0, w1, 16, 16
            ret
    f2:
            neg     w1, w0
            sbfx    x0, x0, 16, 16
            bfi     w0, w1, 16, 16
            ret
    instead, i.e. one insn longer each.  With this patch we get:
    f1:
            mov     w1, w0
            neg     w0, w1, asr 16
            bfi     w0, w1, 16, 16
            ret
    f2:
            neg     w1, w0
            extr    w0, w1, w0, 16
            ret
    i.e. identical f2 and same number of insns as in GCC8 in f1.
    The combiner unfortunately doesn't try splitters when doing 2 -> 1
    combination, so it can't be implemented as combine splitters, but
    it could be implemented as define_insn_and_split if desirable.

    2021-04-16  Jakub Jelinek  <jakub@redhat.com>

            PR target/100075
            * config/aarch64/aarch64.md (*neg_asr_si2_extr, *extrsi5_insn_di):
New
            define_insn patterns.

            * gcc.target/aarch64/pr100075.c: New test.

  parent reply	other threads:[~2021-04-16 11:45 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-14  0:09 [Bug target/100075] New: " luc.vanoostenryck at gmail dot com
2021-04-14  6:55 ` [Bug target/100075] " rguenth at gcc dot gnu.org
2021-04-14 14:54 ` jakub at gcc dot gnu.org
2021-04-16 11:45 ` cvs-commit at gcc dot gnu.org [this message]
2021-04-16 11:45 ` [Bug target/100075] [9/10 " jakub at gcc dot gnu.org
2021-04-16 15:16 ` luc.vanoostenryck at gmail dot com
2021-04-19 13:27 ` cvs-commit at gcc dot gnu.org
2021-04-30  8:10 ` rguenth at gcc dot gnu.org
2021-06-01  8:20 ` rguenth at gcc dot gnu.org
2022-05-27  9:45 ` [Bug target/100075] [10 " rguenth at gcc dot gnu.org
2022-06-28 10:44 ` jakub at gcc dot gnu.org
2023-07-07  9:35 ` rguenth at gcc dot gnu.org

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