[Bug target/100106] [10 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e

["cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106

--- Comment #10 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Alexandre Oliva <aoliva@gcc.gnu.org>:

https://gcc.gnu.org/g:d6b756447cd58bcca20e6892790582308b869817

commit r14-1187-gd6b756447cd58bcca20e6892790582308b869817
Author: Alexandre Oliva <oliva@adacore.com>
Date:   Wed May 24 03:07:56 2023 -0300

    [PR100106] Reject unaligned subregs when strict alignment is required

    The testcase for pr100106, compiled with optimization for 32-bit
    powerpc -mcpu=604 with -mstrict-align expands the initialization of a
    union from a float _Complex value into a load from an SCmode
    constant pool entry, aligned to 4 bytes, into a DImode pseudo,
    requiring 8-byte alignment.

    The patch that introduced the testcase modified simplify_subreg to
    avoid changing the MEM to outermode, but simplify_gen_subreg still
    creates a SUBREG or a MEM that would require stricter alignment than
    MEM's, and lra_constraints appears to get confused by that, repeatedly
    creating unsatisfiable reloads for the SUBREG until it exceeds the
    insn count.

    Avoiding the unaligned SUBREG, expand splits the DImode dest into
    SUBREGs and loads each SImode word of the constant pool with the
    proper alignment.


    for  gcc/ChangeLog

            PR target/100106
            * emit-rtl.cc (validate_subreg): Reject a SUBREG of a MEM that
            requires stricter alignment than MEM's.

    for  gcc/testsuite/ChangeLog

            PR target/100106
            * gcc.target/powerpc/pr100106-sa.c: New.