From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 20E783891C1F; Fri, 16 Apr 2021 07:09:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 20E783891C1F From: "rguenth at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/100106] [10/11 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e Date: Fri, 16 Apr 2021 07:09:09 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 11.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: rguenth at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 10.4 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_status everconfirmed priority cf_reconfirmed_on Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Apr 2021 07:09:10 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D100106 Richard Biener changed: What |Removed |Added ---------------------------------------------------------------------------- Status|UNCONFIRMED |NEW Ever confirmed|0 |1 Priority|P3 |P2 Last reconfirmed| |2021-04-16 --- Comment #1 from Richard Biener --- Confirmed. #1 0x0000000001d9f1c5 in gen_movdi (operand0=3D0x7ffff63ae390,=20 operand1=3D0x7ffff63ae480) at /home/rguenther/src/trunk/gcc/config/arm/arm.md:6187 6187 gcc_checking_assert (aligned_operand (operands[1], DImode)); (gdb) p debug_rtx (operands[1]) (mem/u/c:DI (reg/f:SI 114) [0 S8 A32]) I think the bug is that /* Use the subreg machinery either to narrow OP0 to the required words or to cope with mode punning between equal-sized modes. In the latter case, use subreg on the rhs side, not lhs. */ rtx sub; HOST_WIDE_INT regnum; poly_uint64 regsize =3D REGMODE_NATURAL_SIZE (GET_MODE (op0)); if (known_eq (bitnum, 0U) && known_eq (bitsize, GET_MODE_BITSIZE (GET_MODE (op0)))) { sub =3D simplify_gen_subreg (GET_MODE (op0), value, fieldmode, 0); if (sub) { if (reverse) sub =3D flip_storage_order (GET_MODE (op0), sub); here simplify_gen_subreg simplifies (subreg:DI ((mem/u/c:SC (reg/f:SI 114) = [0=20 S8 A32])) to (mem/u/c:DI (reg/f:SI 114) [0 S8 A32]) but SCmode has different alignment requirement than DImode.=