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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/100165] fmov could be used to zero out the upper bits instead of movi/zip or movi/ins with __builtin_shuffle and zero vector Date: Tue, 27 Feb 2024 08:44:38 +0000 [thread overview] Message-ID: <bug-100165-4-MBzlVXsDTh@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-100165-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100165 --- Comment #5 from Andrew Pinski <pinskia at gcc dot gnu.org> --- For the ones which produce ins, it should be easy to modify the pattern to emit fmov for those cases, that is `elt == 0`: (define_insn "aarch64_simd_vec_set_zero<mode>" [(set (match_operand:VALLS_F16 0 "register_operand" "=w") (vec_merge:VALLS_F16 (match_operand:VALLS_F16 1 "aarch64_simd_imm_zero" "") (match_operand:VALLS_F16 3 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] "TARGET_SIMD && exact_log2 (INTVAL (operands[2])) >= 0" { int elt = ENDIAN_LANE_N (<nunits>, exact_log2 (INTVAL (operands[2]))); operands[2] = GEN_INT ((HOST_WIDE_INT) 1 << elt); return "ins\\t%0.<Vetype>[%p2], <vwcore>zr"; } )
prev parent reply other threads:[~2024-02-27 8:44 UTC|newest] Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-21 0:47 [Bug target/100165] New: " pinskia at gcc dot gnu.org 2021-08-25 8:13 ` [Bug target/100165] " pinskia at gcc dot gnu.org 2023-11-12 21:27 ` pinskia at gcc dot gnu.org 2023-11-12 21:32 ` pinskia at gcc dot gnu.org 2023-11-12 21:45 ` pinskia at gcc dot gnu.org 2023-11-12 21:45 ` pinskia at gcc dot gnu.org 2024-02-27 8:44 ` pinskia at gcc dot gnu.org [this message]
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