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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/100165] fmov could be used to zero out the upper bits
 instead of movi/zip or movi/ins with __builtin_shuffle and zero vector
Date: Tue, 27 Feb 2024 08:44:38 +0000
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X-Bugzilla-Keywords: missed-optimization
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D100165

--- Comment #5 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
For the ones which produce ins, it should be easy to modify the pattern to =
emit
fmov for those cases, that is `elt =3D=3D 0`:

(define_insn "aarch64_simd_vec_set_zero<mode>"
  [(set (match_operand:VALLS_F16 0 "register_operand" "=3Dw")
        (vec_merge:VALLS_F16
            (match_operand:VALLS_F16 1 "aarch64_simd_imm_zero" "")
            (match_operand:VALLS_F16 3 "register_operand" "0")
            (match_operand:SI 2 "immediate_operand" "i")))]
  "TARGET_SIMD && exact_log2 (INTVAL (operands[2])) >=3D 0"
  {
    int elt =3D ENDIAN_LANE_N (<nunits>, exact_log2 (INTVAL (operands[2])));
    operands[2] =3D GEN_INT ((HOST_WIDE_INT) 1 << elt);
    return "ins\\t%0.<Vetype>[%p2], <vwcore>zr";
  }
)=