[Bug target/100266] New: [RISCV] Provide programmatic implementation of CAS

[Bug target/100266] New: [RISCV] Provide programmatic implementation of CAS

[christophm30 at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100266

            Bug ID: 100266
           Summary: [RISCV] Provide programmatic implementation of CAS
           Product: gcc
           Version: unknown
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: christophm30 at gmail dot com
  Target Milestone: ---

At the moment CAS is implemented in form of a hard-coded sequence in sync.md.
When implementing this in a programmatic way (i.e. in riscv.c) we can make this
code much more maintainable. Moving this into C-code also allows to properly
emit the proper fences for ensuring the required memory ordering.

To do so we need to basically do the following:
* model LR and SC INSNs
* implement riscv_expand_compare_and_swap () in riscv.c

[Bug target/100266] [RISCV] Provide programmatic implementation of CAS

[christophm30 at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100266

--- Comment #1 from Christoph M. <christophm30 at gmail dot com> ---
A patchset to resolve this can be found here:
  https://gcc.gnu.org/pipermail/gcc-patches/2021-April/568684.html

[Bug target/100266] [RISCV] Provide programmatic implementation of CAS

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100266

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jim Wilson <wilson@gcc.gnu.org>:

https://gcc.gnu.org/g:e1fcf14f33e4f371aae8ae497ca58a760d53ca6d

commit r12-527-ge1fcf14f33e4f371aae8ae497ca58a760d53ca6d
Author: Christoph Muellner <cmuellner@gcc.gnu.org>
Date:   Wed May 5 21:23:41 2021 +0200

    RISC-V: Generate helpers for cbranch4.

    On RISC-V we are facing the fact, that our conditional branches
    require Pmode conditions. Currently, we generate them explicitly
    with a check for Pmode and then calling the proper generator
    (i.e. gen_cbranchdi4 on RV64 and gen_cbranchsi4 on RV32).
    Let's simplify this code by generating the INSN helpers
    and use gen_cbranch4 (Pmode).

            gcc/
            PR target/100266
            * config/riscv/riscv.c (riscv_block_move_loop): Use cbranch helper.
            * config/riscv/riscv.md (cbranch<mode>4): Generate helpers.
            (stack_protect_test): Use cbranch helper.