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From: "linkw at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug rtl-optimization/100328] IRA doesn't model matching constraint
 well
Date: Mon, 28 Jun 2021 05:25:25 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D100328

--- Comment #6 from Kewen Lin <linkw at gcc dot gnu.org> ---
Created attachment 51066
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=3D51066&action=3Dedit
aarch64 XPASS failure list

The patch v3 bootstrapped and regression-tested on x86_64-redhat-linux and
powerpc64le-linux-gnu, but still have some "XFAIL -> XPASS" regression fail=
ures
on aarch64-linux-gnu, I think these remaining failures are expected (assemb=
ly
gets improved). Need Richard's help to double check/confirm them.

For example, for div_f16.c, mad_f32.c and sub_f64.c, the related different
assembly looks like below:

BEFORE:

div_h4_f16_x_untied:

        mov     z4.h, h4
        movprfx z0, z1
        fdiv    z0.h, p0/m, z0.h, z4.h
        ret

mad_s4_f32_x_untied:

        mov     z4.s, s4
        movprfx z0, z4
        fmla    z0.s, p0/m, z1.s, z2.s
        ret

sub_d4_f64_x_untied:

        mov     z4.d, d4
        movprfx z0, z1
        fsub    z0.d, p0/m, z0.d, z4.d
        ret

AFTER:

div_h4_f16_x_untied:

        mov     z0.h, h4
        fdivr   z0.h, p0/m, z0.h, z1.h
        ret

mad_s4_f32_x_untied:

        mov     z0.s, s4
        fmla    z0.s, p0/m, z1.s, z2.s
        ret

sub_d4_f64_x_untied:

        mov     z0.d, d4
        fsubr   z0.d, p0/m, z0.d, z1.d
        ret

The assembly with this patch saves movprfx.=