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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/100378] [9/10/11/12 Regression] arm64: lsl + asr used
 instead of sxth
Date: Sun, 02 May 2021 02:32:07 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D100378

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Last reconfirmed|                            |2021-05-02
             Status|UNCONFIRMED                 |NEW
     Ever confirmed|0                           |1

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Trying 2 -> 6:
    2: r94:DI=3Dr96:DI
      REG_DEAD r96:DI
    6: r95:SI=3Dsign_extend(r94:DI#0)
      REG_DEAD r94:DI
Failed to match this instruction:
(set (reg:SI 95 [ s ])
    (ashiftrt:SI (subreg:SI (ashift:DI (reg:DI 96)
                (const_int 16 [0x10])) 0)
        (const_int 16 [0x10])))

So what is happening is now combine is inserting an extra mov from x0 to a =
new
register 96 and when it does the combine, it does it badly not into what it=
 was
before:
(insn 6 3 11 2 (set (reg:SI 95 [ s ])
        (sign_extend:SI (subreg:HI (reg/v:DI 94 [ s ]) 0))) "t8877.c":6:37 =
111
{*extendhisi2_aarch64}
     (expr_list:REG_DEAD (reg/v:DI 94 [ s ])
        (nil)))

Confirmed.  I thought there was a dup of this bug somewhere but I cannot fi=
nd
it.=