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From: "ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/100445] [12 Regression] ice during RTL pass: vregs
Date: Thu, 06 May 2021 12:57:30 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D100445

--- Comment #5 from Uro=C5=A1 Bizjak <ubizjak at gmail dot com> ---
ix86_expand_sse_movcc has special TARGET_XOP path, so the following patch is
needed:

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 347295afbb5..667dd057e0d 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1687,6 +1687,17 @@ (define_expand "vcondu<mode><mode>"
   DONE;
 })

+;; XOP parallel XMM conditional moves
+(define_insn "*mmx_pcmov<mode>"
+  [(set (match_operand:MMXMODEI 0 "register_operand" "=3Dx")
+       (if_then_else:MMXMODEI
+         (match_operand:MMXMODEI 3 "register_operand" "x")
+         (match_operand:MMXMODEI 1 "register_operand" "x")
+         (match_operand:MMXMODEI 2 "register_operand" "x")))]
+  "TARGET_MMX_WITH_SSE && TARGET_XOP"
+  "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
+  [(set_attr "type" "sse4arg")])
+
 (define_expand "vcond_mask_<mode><mode>"
   [(set (match_operand:MMXMODEI 0 "register_operand")
        (vec_merge:MMXMODEI=