From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id E5C66384F002; Wed, 14 Sep 2022 08:23:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E5C66384F002 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1663143830; bh=gKRmLAFUF3oKcDP4TIy+reX7SLxzTcFWrKQYnDC3eio=; h=From:To:Subject:Date:In-Reply-To:References:From; b=GTipZhnu2fTxyCO76A9mtT/HNZfjdfuFq/QHCwFJ8oyRe2WkDQLUDIKEiuRdMmIu9 G5xZTEvmpmyNxgmVV4TxX9DuStCbE7hxBWITQbUGLlNt0kn1NVklWRHrSRO1XlHrzj dUuWNr89nmIn9YAUubNDVbCI/OcU23k2jmutRKiE= From: "linkw at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/100645] ICE in related_vector_mode, at stor-layout.c:537 Date: Wed, 14 Sep 2022 08:23:50 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: linkw at gcc dot gnu.org X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: linkw at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: assigned_to Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D100645 Kewen Lin changed: What |Removed |Added ---------------------------------------------------------------------------- Assignee|unassigned at gcc dot gnu.org |linkw at gcc dot gn= u.org --- Comment #2 from Kewen Lin --- Confirmed. type v2di (vector(2) long long int) goes with TImode with altivec support, which isn't a vector mode, so it fails with: gcc_assert (VECTOR_MODE_P (vector_mode)); The reason why veclower doesn't lower it is that: it can go with vec_shr_op= tab against TImode. /* Also detect vec_shr pattern - VEC_PERM_EXPR with zero vector as VEC1 and a right element shift MASK. */ if (optab_handler (vec_shr_optab, TYPE_MODE (vect_type)) !=3D CODE_FOR_nothing ... One alternative is to guard this check with VECTOR_MODE_P(TYPE_MODE (vect_type)), but someone can argue that target shouldn't support this kind= of optab for one non vector mode. So it's more reasonable to fix it in target code: diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md index b87a742cca8..ed3feee2041 100644 --- a/gcc/config/rs6000/vector.md +++ b/gcc/config/rs6000/vector.md @@ -1532,7 +1532,7 @@ (define_expand "vec_shr_" [(match_operand:VEC_L 0 "vlogical_operand") (match_operand:VEC_L 1 "vlogical_operand") (match_operand:QI 2 "reg_or_short_operand")] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" { rtx bitshift =3D operands[2]; rtx shift; TImode is excluded by VECTOR_UNIT_ALTIVEC_OR_VSX_P check.=