From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id ADF433959E42; Thu, 20 May 2021 11:27:37 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org ADF433959E42 From: "rguenth at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/100701] [12 Regression] wrong code with -O -fschedule-insns2 Date: Thu, 20 May 2021 11:27:37 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: wrong-code X-Bugzilla-Severity: normal X-Bugzilla-Who: rguenth at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 12.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: everconfirmed cf_reconfirmed_on cf_gcctarget bug_status component cc target_milestone Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 20 May 2021 11:27:37 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D100701 Richard Biener changed: What |Removed |Added ---------------------------------------------------------------------------- Ever confirmed|0 |1 Last reconfirmed| |2021-05-20 Target| |x86_64-*-* i?86-*-* Status|UNCONFIRMED |NEW Component|rtl-optimization |target CC| |uros at gcc dot gnu.org Target Milestone|--- |12.0 --- Comment #1 from Richard Biener --- orq %rdi, %rsi pshuflw $0, %xmm3, %xmm0 movq %xmm0, %rbp and %rbx, %rbp je .L4 Confirmed. Somehow the mmx_andv8qi3 doesn't clobber CC: (insn 19 88 15 2 (parallel [ (set (reg:CCZ 17 flags) (compare:CCZ (ior:DI (reg:DI 4 si [158]) (reg:DI 5 di [orig:101 i ] [101])) (const_int 0 [0]))) (clobber (reg:DI 4 si [158])) ]) "t.c":13:6 562 {*iordi_3} (expr_list:REG_DEAD (reg:DI 4 si [158]) (expr_list:REG_UNUSED (reg:DI 4 si [158]) (nil)))) (insn:TI 15 19 89 2 (set (reg:V4HI 20 xmm0 [106]) (vec_duplicate:V4HI (truncate:HI (reg:SI 23 xmm3 [162])))) "t.c":12= :5 1459 {*vec_dupv4hi} (expr_list:REG_DEAD (reg:SI 23 xmm3 [162]) (nil))) (insn:TI 89 15 17 2 (set (reg/v:V8QI 6 bp [orig:95 a ] [95]) (reg:V8QI 20 xmm0 [106])) "t.c":12:5 1302 {*movv8qi_internal} (expr_list:REG_DEAD (reg:V8QI 20 xmm0 [106]) (nil))) (insn:TI 17 89 20 2 (set (reg/v:V8QI 6 bp [orig:95 a ] [95]) (and:V8QI (reg/v:V8QI 6 bp [orig:95 a ] [95]) (reg/v:V8QI 3 bx [orig:98 a ] [98]))) "t.c":12:5 1422 {*mmx_andv8qi3} (nil)) (jump_insn 20 17 25 2 (set (pc) (if_then_else (eq (reg:CCZ 17 flags) (const_int 0 [0])) (label_ref:DI 113) (pc))) "t.c":13:6 822 {*jcc} (expr_list:REG_DEAD (reg:CCZ 17 flags) (int_list:REG_BR_PROB 7 (nil)))=