From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id D5ED03857C7A; Wed, 16 Jun 2021 05:53:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D5ED03857C7A From: "luoxhu at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/100866] PPC: Inefficient code for vec_revb(vector unsigned short) < P9 Date: Wed, 16 Jun 2021 05:53:01 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 8.3.1 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: enhancement X-Bugzilla-Who: luoxhu at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 16 Jun 2021 05:53:01 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D100866 --- Comment #5 from luoxhu at gcc dot gnu.org --- (In reply to Segher Boessenkool from comment #4) > This PR is specifically about the vec_revb builtin. But yes, we should > look at what is generated for all other code (having only the builtin > generate good code is suboptimal for a generic thing like this), and for > other sizes as well. Sorry I don't quite understand what you mean. IMO vec_revb is expanded by CODE_FOR_revb_v8hi through revb_ pattern. So this is where we should change to make better code generation...=20 For V8HI, it is natural to use vspltish 8+vrlh to turn {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15} to {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14}. But for V4SI, we need use vspltish+vrlh to turn it to {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14} first, and a "vrlw 16" to turn it t= o=20 {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12}. I am not sure whether this is bett= er than lvx+xxlnor+vperm especially for V2DI&V1TI with additional "vrld 32" or "vrld 32"+"vrlq 64"? (Those are all operations on register without load from memory like lvx.) bt 5 #0 gen_revb_v8hi (operand0=3D0x7ffff4d4ce40, operand1=3D0x7ffff4d4cf60) at ../../gcc/gcc/config/rs6000/vsx.md:5858 #1 0x0000000010b05360 in insn_gen_fn::operator() (this=3D0x130ab188 ) at../../gcc/gcc/recog.h:407 #2 0x0000000011aa1e30 in rs6000_expand_unop_builtin (icode=3DCODE_FOR_revb= _v8hi, exp=3D , target=3D0x7ffff4d4ce40) at ../../gcc/gcc/config/rs6000/rs6000-call.c:9451 #3 0x0000000011ab27a4 in rs6000_expand_builtin (exp=3D, target=3D0x7ffff4d4ce40, subtarget=3D0x0, mode=3DE_V8HImod= e, ignore=3D0) at ../../gcc/gcc/config/rs6000/rs6000-call.c:13157 #4 0x0000000010815268 in expand_builtin (exp=3D, target=3D0x7ffff4d4ce40, subtarget=3D0x0, mode=3DE_V8HImode, ignore=3D0) at ../../gcc/gcc/builtins.c:9559=