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From: "crazylht at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/100885] [12 Regression] ICE: in extract_constrain_insn, at recog.c:2671: insn does not satisfy its constraints: {sse4_1_zero_extendv8qiv8hi2}
Date: Thu, 03 Jun 2021 03:49:49 +0000	[thread overview]
Message-ID: <bug-100885-4-eTso902av3@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-100885-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100885

--- Comment #2 from Hongtao.liu <crazylht at gmail dot com> ---

> With avx512vl Yw should be matched, and w/o avx512bw, only SSE_REGS should
> be matched, why xmm16 is allocated?

It didn't come from RA, but post_reload splitter.

18103(define_insn_and_split "*sse4_1_zero_extendv8qiv8hi2_3"
18104  [(set (match_operand:V16QI 0 "register_operand" "=Yr,*x,v")
18105        (vec_select:V16QI
18106          (vec_concat:V32QI
18107            (match_operand:V16QI 1 "vector_operand" "YrBm,*xBm,vm")
18108            (match_operand:V16QI 2 "const0_operand" "C,C,C"))
18109          (match_parallel 3 "pmovzx_parallel"
18110            [(match_operand 4 "const_int_operand" "n,n,n")])))]
18111  "TARGET_SSE4_1"

  parent reply	other threads:[~2021-06-03  3:49 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-02 20:51 [Bug target/100885] New: " zsojka at seznam dot cz
2021-06-03  3:33 ` [Bug target/100885] " crazylht at gmail dot com
2021-06-03  3:49 ` crazylht at gmail dot com [this message]
2021-06-03  5:10 ` crazylht at gmail dot com
2021-06-03  7:14 ` crazylht at gmail dot com
2021-06-03 10:40 ` crazylht at gmail dot com
2021-06-07  3:28 ` cvs-commit at gcc dot gnu.org
2021-06-07  4:38 ` cvs-commit at gcc dot gnu.org
2021-06-07  4:41 ` crazylht at gmail dot com
2021-06-07  9:04 ` rguenth at gcc dot gnu.org
2021-06-07 14:49 ` cvs-commit at gcc dot gnu.org
2021-06-07 14:59 ` cvs-commit at gcc dot gnu.org

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