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From: "carll at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/100930] PPC: Missing builtins for P9 vextsb2w, vextsb2w,  vextsb2d, vextsh2d, vextsw2d
Date: Sat, 29 Jan 2022 00:55:05 +0000	[thread overview]
Message-ID: <bug-100930-4-z84boHlVSg@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-100930-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100930

Carl Love <carll at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |carll at gcc dot gnu.org

--- Comment #3 from Carl Love <carll at gcc dot gnu.org> ---
So, with a little archaeological digging......

Looks like the patch was committed to mainline on 6/8/2021 as follows:

 From db042e1603db5057314c404eded73c45f60ad2d6 Mon Sep 17 00:00:00 2001
From: Carl Love <cel@us.ibm.com>
Date: Mon, 3 Feb 2020 14:41:42 -0600
Subject: [PATCH] RS6000 Add 128-bit Binary Integer sign extend operations

This patch adds the 128-bit sign extension instruction support and
corresponding builtin support.

RS6000 Add 128-bit Binary Integer sign extend operations

2021-06-08  Carl Love  <cel@us.ibm.com>

gcc/ChangeLog

        * config/rs6000/altivec.h (vec_signextll, vec_signexti, vec_signextq):
        Add define for new builtins.
        * config/rs6000/altivec.md(altivec_vreveti2): Add define_expand.
        * config/rs6000/rs6000-builtin.def (VSIGNEXTI, VSIGNEXTLL):  Add
        overloaded builtin definitions.
        (VSIGNEXTSB2W, VSIGNEXTSH2W, VSIGNEXTSB2D, VSIGNEXTSH2D,VSIGNEXTSW2D,
        VSIGNEXTSD2Q):  Add builtin expansions.
        (SIGNEXT): Add P10 overload definition.
        * config/rs6000/rs6000-call.c (P9V_BUILTIN_VEC_VSIGNEXTI,
P9V_BUILTIN_VEC_VSIGNEXTLL,
        P10_BUILTIN_VEC_SIGNEXT): Add overloaded argument definitions.
        * config/rs6000/vsx.md (vsx_sign_extend_v2di_v1ti): Add define_insn.
        (vsignextend_v2di_v1ti, vsignextend_qi_<mode>, vsignextend_hi_<mode>,
        vsignextend_si_v2di)[VIlong]: Add define_expand.
        Make define_insn vsx_sign_extend_si_v2di visible.
        * doc/extend.texi:  Add documentation for the vec_signexti,
        vec_signextll builtins and vec_signextq.

gcc/testsuite/ChangeLog

        * gcc.target/powerpc/int_128bit-runnable.c (extsd2q): Update expected
        count.
        Add tests for vec_signextq.
        * gcc.target/powerpc/p9-sign_extend-runnable.c:  New test case.


Looking at the GCC 11 tree it looks like I did backport and commit it there as
well:

commit 88b66b376844fe7c537ab229250a41a54e706eaf
Author: Carl Love <cel@us.ibm.com>
Date:   Tue Jun 15 11:37:31 2021 -0500

    RS6000 Add 128-bit Binary Integer sign extend operations

    This patch adds the 128-bit sign extension instruction support and
    corresponding builtin support.

    RS6000 Add 128-bit Binary Integer sign extend operations

    2021-06-08  Carl Love  <cel@us.ibm.com>

    gcc/ChangeLog

            * config/rs6000/altivec.h (vec_signextll, vec_signexti,
vec_signext\
q):
            Add define for new builtins.
            * config/rs6000/altivec.md(altivec_vreveti2): Add define_expand.
            * config/rs6000/rs6000-builtin.def (VSIGNEXTI, VSIGNEXTLL):  Add
            overloaded builtin definitions.
            (VSIGNEXTSB2W, VSIGNEXTSH2W, VSIGNEXTSB2D,
VSIGNEXTSH2D,VSIGNEXTSW2\
D,
            VSIGNEXTSD2Q):  Add builtin expansions.
            (SIGNEXT): Add P10 overload definition.
            * config/rs6000/rs6000-call.c (P9V_BUILTIN_VEC_VSIGNEXTI,
            P9V_BUILTIN_VEC_VSIGNEXTLL, P10_BUILTIN_VEC_SIGNEXT): Add
            overloaded argument definitions.
            * config/rs6000/vsx.md (vsx_sign_extend_v2di_v1ti): Add
define_insn\
.
            (vsignextend_v2di_v1ti, vsignextend_qi_<mode>,
vsignextend_hi_<mode\
>,
            vsignextend_si_v2di)[VIlong]: Add define_expand.
            Make define_insn vsx_sign_extend_si_v2di visible.
            * doc/extend.texi:  Add documentation for the vec_signexti,
            vec_signextll builtins and vec_signextq.

    gcc/testsuite/ChangeLog

            * gcc.target/powerpc/int_128bit-runnable.c (extsd2q): Update
expect\
ed
            count.
            Add tests for vec_signextq.
            * gcc.target/powerpc/p9-sign_extend-runnable.c:  New test case.


Probably should have fixed the commit log date. 

So, it looks to me like this has been done and the issue should be closed.

  parent reply	other threads:[~2022-01-29  0:55 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-06 10:27 [Bug target/100930] New: " jens.seifert at de dot ibm.com
2021-06-06 21:00 ` [Bug target/100930] " wschmidt at gcc dot gnu.org
2021-06-10 14:17 ` wschmidt at gcc dot gnu.org
2022-01-29  0:55 ` carll at gcc dot gnu.org [this message]
2022-01-31 14:49 ` wschmidt at gcc dot gnu.org

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