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Subject: [Bug rtl-optimization/101076] RTL Combine pass won't generate
 sign_extnd RTX in some senario
Date: Tue, 15 Jun 2021 06:31:30 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D101076

--- Comment #2 from Coco Wang <wf831130 at sina dot com> ---
(In reply to Andrew Pinski from comment #1)
> What target is this for?
> For both x86_64 and aarch64 we have both shifts in SI mode so we don't end
> up with problem.
> We get the following RTL for aarch64 (before combine):
> (insn 6 3 7 2 (set (reg:SI 96)
>         (ashift:SI (reg/v:SI 94 [ a ])
>             (const_int 16 [0x10]))) "t551.c":3:15 692
> {*aarch64_ashl_sisd_or_int_si3}
>      (expr_list:REG_DEAD (reg/v:SI 94 [ a ])
>         (nil)))
> (insn 7 6 12 2 (set (reg:SI 95)
>         (ashiftrt:SI (reg:SI 96)
>             (const_int 16 [0x10]))) "t551.c":3:22 696
> {*aarch64_ashr_sisd_or_int_si3}
>      (expr_list:REG_DEAD (reg:SI 96)
>         (nil)))
>=20
> And then we get:
> Trying 6 -> 7:
>     6: r96:SI=3Dr97:SI<<0x10
>       REG_DEAD r97:SI
>     7: r95:SI=3Dr96:SI>>0x10
>       REG_DEAD r96:SI
> Successfully matched this instruction:
> (set (reg:SI 95)
>     (sign_extend:SI (subreg:HI (reg:SI 97) 0)))
> In combine.
>=20
>=20
> I Noticed you have:
> r76:SI=3Dr78:DI#0<<0x10
> 7: r75:SI=3Dr76:SI>>0x10
>=20
> In combine, so you have a subreg of r78, where is the subreg produced ...

The target is RISCV64, I will check the reason why there is a subreg produc=
ed.=