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From: "wf831130 at sina dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/101076] RTL Combine pass won't generate sign_extnd RTX in some senario
Date: Tue, 15 Jun 2021 06:53:40 +0000 [thread overview]
Message-ID: <bug-101076-4-fsT7Sl6sWQ@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-101076-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101076
--- Comment #4 from Coco Wang <wf831130 at sina dot com> ---
(In reply to Andrew Pinski from comment #3)
> This sounds like a rsicv backend issue really ...
I think the key is the subreg, the reason why x86_64 and aarch64 have no
problems is that subreg does not appear in RTL.
The code of this part is not right
if (!OBJECT_P (lhs)
&& ! (GET_CODE (lhs) == SUBREG
&& (OBJECT_P (SUBREG_REG (lhs))))
&& CONST_INT_P (rhs)
&& INTVAL (rhs) >= 0
&& INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
&& INTVAL (rhs) < mode_width
&& (new_rtx = extract_left_shift (mode, lhs, INTVAL (rhs))) != 0)
new_rtx = make_extraction (mode, make_compound_operation (new_rtx,
next_code),
0, NULL_RTX, mode_width - INTVAL (rhs),
code == LSHIFTRT, 0, in_code == COMPARE);
next prev parent reply other threads:[~2021-06-15 6:53 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-15 3:37 [Bug rtl-optimization/101076] New: " wf831130 at sina dot com
2021-06-15 6:14 ` [Bug rtl-optimization/101076] " pinskia at gcc dot gnu.org
2021-06-15 6:31 ` wf831130 at sina dot com
2021-06-15 6:41 ` pinskia at gcc dot gnu.org
2021-06-15 6:53 ` wf831130 at sina dot com [this message]
2021-06-15 7:01 ` pinskia at gcc dot gnu.org
2023-06-02 5:25 ` pinskia at gcc dot gnu.org
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