From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 69469385740E; Tue, 15 Jun 2021 03:37:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 69469385740E From: "wf831130 at sina dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/101076] New: RTL Combine pass won't generate sign_extnd RTX in some senario Date: Tue, 15 Jun 2021 03:37:27 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: new X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: wf831130 at sina dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_id short_desc product version bug_status bug_severity priority component assigned_to reporter target_milestone Message-ID: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 15 Jun 2021 03:37:28 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D101076 Bug ID: 101076 Summary: RTL Combine pass won't generate sign_extnd RTX in some senario Product: gcc Version: 12.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: wf831130 at sina dot com Target Milestone: --- I found a little bug in the combine pass. When I use 64bit gcc to compile the below test.c, I found some issue cat test.c int test(int a) { return (a << 16) >> 16; } In the combine pass, the log shows Trying 6 -> 7: 6: r76:SI=3Dr78:DI#0<<0x10 REG_DEAD r78:DI 7: r75:SI=3Dr76:SI>>0x10 REG_DEAD r76:SI Failed to match this instruction: (set (reg:SI 75) (ashiftrt:SI (subreg:SI (ashift:DI (reg:DI 78) (const_int 16 [0x10])) 0) (const_int 16 [0x10]))) Then I debugged and checkd the gcc code and fonud some issue in the function make_compound_operation_int which is in the combine.c,=20 case ASHIFTRT: lhs =3D XEXP (x, 0); rhs =3D XEXP (x, 1); /* If we have (ashiftrt (ashift foo C1) C2) with C2 >=3D C1, this is a SIGN_EXTRACT. */ if (CONST_INT_P (rhs) && GET_CODE (lhs) =3D=3D ASHIFT && CONST_INT_P (XEXP (lhs, 1)) && INTVAL (rhs) >=3D INTVAL (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) >=3D 0 && INTVAL (rhs) < mode_width) { new_rtx =3D make_compound_operation (XEXP (lhs, 0), next_code); new_rtx =3D make_extraction (mode, new_rtx, INTVAL (rhs) - INTVAL (XEXP (lhs, 1)), NULL_RTX, mode_width - INTVAL (rhs), code =3D=3D LSHIFTRT, 0, in_code =3D= =3D COMPARE); break; } /* See if we have operations between an ASHIFTRT and an ASHIFT. If so, try to merge the shifts into a SIGN_EXTEND. We could also do this for some cases of SIGN_EXTRACT, but it doesn't seem worth the effort; the case checked for occurs on Alpha. */ if (!OBJECT_P (lhs) && ! (GET_CODE (lhs) =3D=3D SUBREG && (OBJECT_P (SUBREG_REG (lhs)))) && CONST_INT_P (rhs) && INTVAL (rhs) >=3D 0 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT && INTVAL (rhs) < mode_width && (new_rtx =3D extract_left_shift (mode, lhs, INTVAL (rhs))) != =3D 0) new_rtx =3D make_extraction (mode, make_compound_operation (new_rtx, next_code= ), 0, NULL_RTX, mode_width - INTVAL (rhs), code =3D=3D LSHIFTRT, 0, in_code =3D=3D = COMPARE); break; The issue code is "(new_rtx =3D extract_left_shift (mode, lhs, INTVAL (rhs)= )) !=3D 0)", this part wants to extract_left_shift information, but the second input parameter lhs is not right, it's still SUBREG, but it should transmit ash= ift part into the function. So the second parameter "lhs" should change to "XEXP (lhs, 0)". After change this issue, we can get the right combine result(sign_extend): Trying 6 -> 7: 6: r138:SI=3Dr140:DI#0<<0x10 REG_DEAD r140:DI 7: r137:SI=3Dr138:SI>>0x10 REG_DEAD r138:SI Successfully matched this instruction: (set (reg:SI 137) (sign_extend:SI (subreg:HI (reg:DI 140) 0))) allowing combination of insns 6 and 7 original costs 4 + 4 =3D 8 replacement cost 8 deferring deletion of insn with uid =3D 6. modifying insn i3 7: r137:SI=3Dsign_extend(r140:DI#0) REG_DEAD r140:DI deferring rescan insn with uid =3D 7.=