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Subject: [Bug target/101175] builtin_clz generates wrong bsr instruction
Date: Wed, 23 Jun 2021 10:51:45 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D101175

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:1e16f2b472c7d253d564556a048dc4ae16119c00

commit r12-1743-g1e16f2b472c7d253d564556a048dc4ae16119c00
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Wed Jun 23 12:50:53 2021 +0200

    i386: Prevent unwanted combine from LZCNT to BSR [PR101175]

    The current RTX pattern for BSR allows combine pass to convert LZCNT in=
sn
    to BSR. Note that the LZCNT has a defined behavior to return the operand
    size when operand is zero, where BSR has not.

    Add a BSR specific setting of zero-flag to RTX pattern of BSR insn
    in order to avoid matching unwanted combinations.

    2021-06-23  Uro=C3=85=C2=A1 Bizjak  <ubizjak@gmail.com>

    gcc/
            PR target/101175
            * config/i386/i386.md (bsr_rex64): Add zero-flag setting RTX.
            (bsr): Ditto.
            (*bsrhi): Remove.
            (clz<mode>2): Update RTX pattern for additions.

    gcc/testsuite/

            PR target/101175
            * gcc.target/i386/pr101175.c: New test.=