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From: "crazylht at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/101185] pr96814.c failed after r12-1669 on non-avx512
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Date: Thu, 24 Jun 2021 01:56:38 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D101185

--- Comment #3 from Hongtao.liu <crazylht at gmail dot com> ---
(In reply to Hongtao.liu from comment #1)
> Alloc order is just another kind of cost which can be compensated by
> increasing cost of mask->integer and integer->mask.
>=20
> With below patch , pr96814 wouldn't generate any mask intructions execept
> for=20
>=20
> 	kmovd	%eax, %k1
> 	vpcmpeqd	%ymm1, %ymm1, %ymm1
> 	vmovdqu8	%ymm1, %ymm0{%k1}{z}
>=20
> which is what we want.
>=20
>=20
> modified   gcc/config/i386/i386.md
> @@ -1335,7 +1335,7 @@
>  (define_insn "*cmp<mode>_ccz_1"
>    [(set (reg FLAGS_REG)
>  	(compare (match_operand:SWI1248_AVX512BWDQ_64 0
> -			"nonimmediate_operand" "<r>,?m<r>,$k")
> +			"nonimmediate_operand" "<r>,?m<r>,*k")
>  		 (match_operand:SWI1248_AVX512BWDQ_64 1 "const0_operand")))]
>    "TARGET_AVX512F && ix86_match_ccmode (insn, CCZmode)"
>    "@
> modified   gcc/config/i386/x86-tune-costs.h
> @@ -2768,7 +2768,7 @@ struct processor_costs intel_cost =3D {
>    {6, 6, 6, 6, 6},			/* cost of storing SSE registers
>  					   in 32,64,128,256 and 512-bit */
>    4, 4,				/* SSE->integer and integer->SSE moves */
> -  4, 4,				/* mask->integer and integer->mask moves */
> +  6, 6,				/* mask->integer and integer->mask moves */
I changed intel_cost just to validate 1 unit more cost is also enough for
-mtune=3Dintel to prevent generation of mask instructions.=