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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/101200] Unneeded AND after shift Date: Thu, 24 Jun 2021 20:50:46 +0000 [thread overview] Message-ID: <bug-101200-4-a1CgILuS5H@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-101200-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101200 Andrew Pinski <pinskia at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Status|UNCONFIRMED |NEW Ever confirmed|0 |1 Last reconfirmed| |2021-06-24 Target| |x86_64-linux-gnu --- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> --- For aarch64 we get: adrp x1, .LANCHOR0 add x0, x1, :lo12:.LANCHOR0 add x0, x0, 8 ldrb w1, [x1, #:lo12:.LANCHOR0] and x2, x1, 15 ubfx x1, x1, 4, 4 ldr w2, [x0, x2, lsl 2] str w2, [x0, x1, lsl 2] ret Note the shift and and is combined into one instruction (ubfx) but really only a shift instruction is needed. Here we have: Trying 21 -> 22: 21: r112:SI=r92:SI 0>>0x4 REG_DEAD r92:SI 22: r113:DI=sign_extend(r112:SI) REG_DEAD r112:SI Successfully matched this instruction: (set (reg:DI 113) (zero_extract:DI (subreg:DI (reg:SI 92 [ d.0_1 ]) 0) (const_int 4 [0x4]) (const_int 4 [0x4]))) The multiple modes issue is part of the problem. If I was redesigning the backends, I would only allow DI mode (and SI mode for i386) and always have the zero extends on loads.
next prev parent reply other threads:[~2021-06-24 20:50 UTC|newest] Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-24 20:19 [Bug tree-optimization/101200] New: " steinar+gcc at gunderson dot no 2021-06-24 20:37 ` [Bug rtl-optimization/101200] " pinskia at gcc dot gnu.org 2021-06-24 20:45 ` pinskia at gcc dot gnu.org 2021-06-24 20:50 ` pinskia at gcc dot gnu.org [this message] 2021-06-25 9:34 ` [Bug target/101200] " jakub at gcc dot gnu.org 2021-06-25 9:38 ` jakub at gcc dot gnu.org 2021-06-25 10:38 ` steinar+gcc at gunderson dot no 2021-06-29 17:40 ` law at gcc dot gnu.org
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