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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/101456] Unnecessary vzeroupper when upper bits of YMM registers already zero
Date: Wed, 28 Jul 2021 14:29:04 +0000	[thread overview]
Message-ID: <bug-101456-4-SOLcRxoNb2@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-101456-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101456

--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by H.J. Lu <hjl@gcc.gnu.org>:

https://gcc.gnu.org/g:9775e465c1fbfc32656de77c618c61acf5bd905d

commit r12-2571-g9775e465c1fbfc32656de77c618c61acf5bd905d
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Tue Jul 27 07:46:04 2021 -0700

    x86: Don't set AVX_U128_DIRTY when zeroing YMM/ZMM register

    There is no SSE <-> AVX transition penalty if the upper bits of YMM/ZMM
    registers are unchanged and YMM/ZMM store doesn't change the upper bits
    of YMM/ZMM registers.

    1. Since zeroing YMM/ZMM register is implemented with zeroing XMM
    register, don't set AVX_U128_DIRTY when zeroing YMM/ZMM register.
    2. Since store doesn't change the INIT state on the upper bits of
    YMM/ZMM register, don't set AVX_U128_DIRTY on store if the source
    of store was never non-zero.

    Here are the vzeroupper count differences on SPEC CPU 2017 with

    -Ofast -march=skylake-avx512

                    Before  After    Diff
    500.perlbench_r 226     225     -0.44%
    502.gcc_r       1263    1103    -12.67%
    503.bwaves_r    14      14      0.00%
    505.mcf_r       29      28      -3.45%
    507.cactuBSSN_r 4651    4628    -0.49%
    508.namd_r      433     432     -0.23%
    510.parest_r    20380   19347   -5.07%
    511.povray_r    495     452     -8.69%
    519.lbm_r       2       2       0.00%
    520.omnetpp_r   5954    5677    -4.65%
    521.wrf_r       12353   12339   -0.11%
    523.xalancbmk_r 13137   13001   -1.04%
    525.x264_r      192     191     -0.52%
    526.blender_r   2515    2366    -5.92%
    527.cam4_r      4601    4583    -0.39%
    531.deepsjeng_r 20      19      -5.00%
    538.imagick_r   898     805     -10.36%
    541.leela_r     427     399     -6.56%
    544.nab_r       74      74      0.00%
    548.exchange2_r 72      72      0.00%
    549.fotonik3d_r 318     318     0.00%
    554.roms_r      558     554     -0.72%
    557.xz_r        79      52      -34.18%

    and performance differences are within noise range.

    gcc/

            PR target/101456
            * config/i386/i386.c (ix86_avx_u128_mode_needed): Don't set
            AVX_U128_DIRTY when all bits are zero.

    gcc/testsuite/

            PR target/101456
            * gcc.target/i386/pr101456-1.c: New test.
            * gcc.target/i386/pr101456-2.c: Likewise.

  parent reply	other threads:[~2021-07-28 14:29 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-14 22:39 [Bug target/101456] New: " hjl.tools at gmail dot com
2021-07-14 22:59 ` [Bug target/101456] " arjan at linux dot intel.com
2021-07-15  0:04 ` hjl.tools at gmail dot com
2021-07-15  0:06 ` hjl.tools at gmail dot com
2021-07-15 14:32 ` hjl.tools at gmail dot com
2021-07-16 12:18 ` hjl.tools at gmail dot com
2021-07-28 14:29 ` cvs-commit at gcc dot gnu.org [this message]
2021-07-28 15:02 ` hjl.tools at gmail dot com
2022-02-15 13:42 ` hjl.tools at gmail dot com
2022-02-16  4:57 ` crazylht at gmail dot com
2022-05-06  8:30 ` jakub at gcc dot gnu.org
2023-05-08 12:22 ` rguenth at gcc dot gnu.org

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