From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id B7398396EC81; Mon, 19 Jul 2021 20:59:40 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B7398396EC81 From: "amacleod at redhat dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug tree-optimization/101511] [12 Regression] ice in query_relation, at value-relation.cc:879 Date: Mon, 19 Jul 2021 20:59:40 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: tree-optimization X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: amacleod at redhat dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 12.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: cc Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Jul 2021 20:59:40 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D101511 Andrew Macleod changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |aldyh at gcc dot gnu.org --- Comment #3 from Andrew Macleod --- The new relation code is dominance based, in the interest of efficiency, it can currently miss the odd equivalence if things are processed in a non-dominance order. Its not incorrect, it just may lead to a missed opportunity. This testcase triggers an assert which checks for this situation. There are numerous UNDEFINED values, and we end up register an equivalences: Registering value_relation (Error_18 =3D=3D _4) (bb4) at Error_18 =3D _4 += Error_13; Registering value_relation (Error_13 =3D=3D _4) (bb2) at Error_13 =3D _4 += Error_9; Not we register the bb4 equivalence first, and then alter register the one= in bb2. As a result, we don't currently update post dominated blocks, so we dont combine these into Error_18, Error_13 and _4 in bb4. When we later check for an equivalence between we detect this anomaly. There is nothing incorrect in allowing it, and we'll do so for now.=20=20 Eventually, when its flushed out better, we'll change this back to an asser= t.=