[Bug target/101609] New: no right shift pattern for vector(2) long long on aarch64

[Bug target/101609] New: no right shift pattern for vector(2) long long on aarch64

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101609

            Bug ID: 101609
           Summary: no right shift pattern for vector(2) long long on
                    aarch64
           Product: gcc
           Version: 12.0
            Status: UNCONFIRMED
          Keywords: missed-optimization
          Severity: enhancement
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: pinskia at gcc dot gnu.org
  Target Milestone: ---
            Target: aarch64*-*-*

Take:
#define SIZE 16
typedef long long veci __attribute__((vector_size(SIZE)));

void f(veci &a, veci &b, veci &c){
  c= a>>b;
}
----- CUT ----
We currently produce:
        ldr     q1, [x1]
        ldr     q0, [x0]
        fmov    d3, d1
        dup     d1, v1.d[1]
        fmov    d2, d0
        dup     d0, v0.d[1]
        neg     d4, d3
        sshl    d4, d2, d4
        neg     d2, d1
        sshl    d2, d0, d2
        fmov    x1, d4
        fmov    x0, d2
        stp     x1, x0, [x2]
        ret
----- CUT ----
But we should be able to do:
        ldr     q0, [x1]
        ldr     q1, [x0]
        neg     v0.2d, v0.2d
        sshl    v0.2d, v1.2d, v0.2d
        str     q0, [x2]

[Bug target/101609] no right shift pattern for vector(2) long long on aarch64

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101609

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Note I found this while looking into PR 56873.

[Bug target/101609] no right shift pattern for vector(2) long long on aarch64

[belagod at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101609

Tejas Belagod <belagod at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Last reconfirmed|                            |2021-07-28
     Ever confirmed|0                           |1
                 CC|                            |belagod at gcc dot gnu.org
             Status|UNCONFIRMED                 |NEW

--- Comment #2 from Tejas Belagod <belagod at gcc dot gnu.org> ---
As you rightly point out, vhsr<mode>3 pattern name seems to be using the wrong
iterator. With the right iterator, it does vectorize a previously unvectorized
loop with uint64 shifts, but still doesn't generate 'vector code' for the
example shown here.

[Bug target/101609] no right shift pattern for vector(2) long long on aarch64

[belagod at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101609

--- Comment #3 from Tejas Belagod <belagod at gcc dot gnu.org> ---
> .. but still doesn't generate 'vector code' for the example shown here.

Actually, it does. I was looking in the wrong place.

[Bug target/101609] no right shift pattern for vector(2) long long on aarch64

[belagod at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101609

Tejas Belagod <belagod at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |ASSIGNED

[Bug target/101609] no right shift pattern for vector(2) long long on aarch64

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101609

--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Tejas Belagod <belagod@gcc.gnu.org>:

https://gcc.gnu.org/g:e2e0b85c1e7cb53fd720df0d09278e3d485c733e

commit r12-2817-ge2e0b85c1e7cb53fd720df0d09278e3d485c733e
Author: Tejas Belagod <tbelagod@arm.com>
Date:   Mon Aug 9 11:33:30 2021 +0100

    PR101609: Use the correct iterator for AArch64 vector right shift pattern

    Loops containing long long shifts fail to vectorize due to the vectorizer
    not being able to recognize long long right shifts. This is due to a bug
    in the iterator used for the vashr and vlshr patterns in aarch64-simd.md.

    2021-08-09  Tejas Belagod  <tejas.belagod@arm.com>

    gcc/ChangeLog
            PR target/101609
            * config/aarch64/aarch64-simd.md (vlshr<mode>3, vashr<mode>3): Use
            the right iterator.

    gcc/testsuite/ChangeLog
            * gcc.target/aarch64/vect-shr-reg.c: New testcase.
            * gcc.target/aarch64/vect-shr-reg-run.c: Likewise.

[Bug target/101609] no right shift pattern for vector(2) long long on aarch64

[belagod at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101609

Tejas Belagod <belagod at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #5 from Tejas Belagod <belagod at gcc dot gnu.org> ---
Fixed on trunk.

[Bug target/101609] no right shift pattern for vector(2) long long on aarch64

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101609

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |12.0