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From: "rearnsha at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/101723] New: arm: incorrect order of .fpu and
 .arch_extension directives leads to unsupported instructions
Date: Mon, 02 Aug 2021 10:48:17 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D101723

            Bug ID: 101723
           Summary: arm: incorrect order of .fpu and .arch_extension
                    directives leads to unsupported instructions
           Product: gcc
           Version: 11.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: rearnsha at gcc dot gnu.org
  Target Milestone: ---

This bug was originally reported against GNU binutils
(https://sourceware.org/bugzilla/show_bug.cgi?id=3D28078), but is really a
problem with the way GCC emits the directives .fpu and .arch_extension.


Alok Parlikar 2021-07-12 04:50:04 UTC

I was trying to build tensorflow-lite v2.5 with a custom toolchain that was
using binutils 2.36.1. The build failed when building the xnnpack project w=
ith
an error:

/tmp/ccMSJOfk.s:380: Error: selected processor does not support `vsdot.s8
q12,q9,d11[0]' in ARM mode

Some of my notes about this issue are here:
https://github.com/google/XNNPACK/issues/1465#issuecomment-877910701

Following is a minimal example to reproduce this:


// file: test.c
#include <arm_neon.h>

int32x2_t test(int32x2_t a, int8x8_t b, int8x8_t c) {
        return vdot_lane_s32(a, b, c, 1);
}
// EOF=