From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 80D2638930FB; Tue, 3 Aug 2021 08:49:14 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 80D2638930FB From: "crazylht at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/101743] [12 Regression] Error: insn does not satisfy its constraints since r12-2640-gf7bf03cf69ccb7dc Date: Tue, 03 Aug 2021 08:49:13 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: crazylht at gmail dot com X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: cc Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Aug 2021 08:49:14 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D101743 Hongtao.liu changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |crazylht at gmail dot com --- Comment #1 from Hongtao.liu --- +;; Eliminate a reg-reg mov by inverting the condition of a cmov (#1). +;; mov r0,r1; dec r0; mov r2,r3; cmov r0,r2 -> dec r1; mov r0,r3; cmov r0,= r1 +(define_peephole2 + [(set (match_operand:SWI248 0 "register_operand") + (match_operand:SWI248 1 "register_operand")) + (parallel [(set (reg FLAGS_REG) (match_operand 5)) + (set (match_dup 0) (match_operand:SWI248 6))]) + (set (match_operand:SWI248 2 "register_operand") + (match_operand:SWI248 3)) + (set (match_dup 0) + (if_then_else:SWI248 (match_operator 4 "ix86_comparison_operator" + [(reg FLAGS_REG) (const_int 0)]) + (match_dup 0) + (match_dup 2)))] + "TARGET_CMOVE + && REGNO (operands[2]) !=3D REGNO (operands[0]) + && REGNO (operands[2]) !=3D REGNO (operands[1]) + && peep2_reg_dead_p (1, operands[1]) + && peep2_reg_dead_p (4, operands[2]) + && !reg_overlap_mentioned_p (operands[0], operands[3])" + [(parallel [(set (match_dup 7) (match_dup 8)) + (set (match_dup 1) (match_dup 9))]) + (set (match_dup 0) (match_dup 3)) + (set (match_dup 0) (if_then_else:SWI248 (match_dup 4) + (match_dup 1) + (match_dup 0)))] +{ + operands[7] =3D SET_DEST (XVECEXP (PATTERN (peep2_next_insn (1)), 0, 0)); + operands[8] =3D replace_rtx (operands[5], operands[0], operands[1]); + operands[9] =3D replace_rtx (operands[6], operands[0], operands[1]); +}) + +;; Eliminate a reg-reg mov by inverting the condition of a cmov (#2). +;; mov r2,r3; mov r0,r1; dec r0; cmov r0,r2 -> dec r1; mov r0,r3; cmov r0,= r1 I guess the below peephole should refine its predicate as general_reg_opera= nd, since x86 support movement between gpr, sse, mask registers. r1 here is very likely sse_reg_operand which result in ICE. +(define_peephole2 + [(set (match_operand:SWI248 2 "register_operand") + (match_operand:SWI248 3)) + (set (match_operand:SWI248 0 "register_operand") + (match_operand:SWI248 1 "register_operand")) + (parallel [(set (reg FLAGS_REG) (match_operand 5)) + (set (match_dup 0) (match_operand:SWI248 6))]) + (set (match_dup 0) + (if_then_else:SWI248 (match_operator 4 "ix86_comparison_operator" + [(reg FLAGS_REG) (const_int 0)]) + (match_dup 0) + (match_dup 2)))] + "TARGET_CMOVE + && REGNO (operands[2]) !=3D REGNO (operands[0]) + && REGNO (operands[2]) !=3D REGNO (operands[1]) + && peep2_reg_dead_p (2, operands[1]) + && peep2_reg_dead_p (4, operands[2]) + && !reg_overlap_mentioned_p (operands[0], operands[3])" + [(parallel [(set (match_dup 7) (match_dup 8)) + (set (match_dup 1) (match_dup 9))]) + (set (match_dup 0) (match_dup 3)) + (set (match_dup 0) (if_then_else:SWI248 (match_dup 4) + (match_dup 1) + (match_dup 0)))] +{ + operands[7] =3D SET_DEST (XVECEXP (PATTERN (peep2_next_insn (2)), 0, 0)); + operands[8] =3D replace_rtx (operands[5], operands[0], operands[1]); + operands[9] =3D replace_rtx (operands[6], operands[0], operands[1]); +}) +=