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From: "crazylht at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/101796] Miss optimization to optimized (vashl op0, (op1:
 const_duplicate_vector)) to (ashl op0 op1_inner)
Date: Fri, 27 Aug 2021 07:34:55 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D101796

--- Comment #4 from Hongtao.liu <crazylht at gmail dot com> ---
(In reply to Andrew Pinski from comment #3)
> Combine is able to do the combine but it fails as it does not match:
> Trying 10, 9 -> 14:
>    10: r92:HI=3D0x3
>     9: r91:V32HI=3Dvec_duplicate(r92:HI)
>       REG_DEAD r92:HI
>       REG_EQUAL const_vector
>    14: r88:V32HI=3Dr96:V8DI#0 0>>r91:V32HI
>       REG_DEAD r96:V8DI
>       REG_DEAD r91:V32HI
> Failed to match this instruction:
> (set (reg:V32HI 88)
>     (lshiftrt:V32HI (subreg:V32HI (reg:V8DI 96) 0)
>         (const_vector:V32HI [
>                 (const_int 3 [0x3]) repeated x32
>             ])))
>=20
> This instruction does not have alt for the dup/const_vect case I think:
> (define_insn "<avx2_avx512>_<insn>v<mode><mask_name>"
>   [(set (match_operand:VI2_AVX512VL 0 "register_operand" "=3Dv")
>         (any_lshift:VI2_AVX512VL
>           (match_operand:VI2_AVX512VL 1 "register_operand" "v")
>           (match_operand:VI2_AVX512VL 2 "nonimmediate_operand" "vm")))]
>   "TARGET_AVX512BW"
>   "vp<vshift>v<ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand=
3>,
> %1, %2}"
>   [(set_attr "type" "sseishft")
>    (set_attr "prefix" "maybe_evex")
>    (set_attr "mode" "<sseinsnmode>")])
>=20
> Note I don't think simplify-rtx will change const_vector to just 3 though.

Yes, it's rejected at
https://gcc.gnu.org/pipermail/gcc-patches/2021-August/576837.html=