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Subject: [Bug target/101846] Improve __builtin_shufflevector emitted code
Date: Thu, 12 Aug 2021 06:03:11 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D101846

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuhongt@gcc.gnu.org>:

https://gcc.gnu.org/g:95e1eca43d106d821720744ac6ff1f5df41a1e78

commit r12-2869-g95e1eca43d106d821720744ac6ff1f5df41a1e78
Author: liuhongt <hongtao.liu@intel.com>
Date:   Wed Aug 11 14:00:00 2021 +0800

    Combine avx_vec_concatv16si and avx512f_zero_extendv16hiv16si2_1 to
avx512f_zero_extendv16hiv16si2_2.

    Add define_insn_and_split to combine avx_vec_concatv16si/2 and
    avx512f_zero_extendv16hiv16si2_1 since the latter already zero_extend
    the upper bits, similar for other patterns which are related to
    pmovzx{bw,wd,dq}.

    It will do optimization like

    -       vmovdqa %ymm0, %ymm0    # 7     [c=3D4 l=3D6]  avx_vec_concatv1=
6si/2
            vpmovzxwd       %ymm0, %zmm0    # 22    [c=3D4 l=3D6]=20
avx512f_zero_extendv16hiv16si2
            ret             # 25    [c=3D0 l=3D1]  simple_return_internal

    gcc/ChangeLog:

            PR target/101846
            * config/i386/sse.md (*avx2_zero_extendv16qiv16hi2_2): New
            post_reload define_insn_and_split.
            (*avx512bw_zero_extendv32qiv32hi2_2): Ditto.
            (*sse4_1_zero_extendv8qiv8hi2_4): Ditto.
            (*avx512f_zero_extendv16hiv16si2_2): Ditto.
            (*avx2_zero_extendv8hiv8si2_2): Ditto.
            (*sse4_1_zero_extendv4hiv4si2_4): Ditto.
            (*avx512f_zero_extendv8siv8di2_2): Ditto.
            (*avx2_zero_extendv4siv4di2_2): Ditto.
            (*sse4_1_zero_extendv2siv2di2_4): Ditto.
            (VI248_256, VI248_512, VI148_512, VI148_256, VI148_128): New
            mode iterator.

    gcc/testsuite/ChangeLog:

            PR target/101846
            * gcc.target/i386/pr101846-1.c: New test.=