From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 589A53849AFE; Thu, 2 May 2024 23:09:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 589A53849AFE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1714691367; bh=cTGYku4QEEEAvxTN8huJqARXzEByCDH0Hbq+zrWrkn4=; h=From:To:Subject:Date:In-Reply-To:References:From; b=yO0haEPNEm7rBl+iQbSk4S6uma5ARxzu2CdJHCt9pH6nWli8w9lD0wsw/4HIYuGRm UzvY4k5ZID3LKgmM7Kyo6gQG0LKwxxMOaWzi3BORaWsLVWzbersKvAOQxYN3koQLLO 8wmu5zHRDgSAR+NQvIW0/vv7qIYBz2/g4izjKXpA= From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/101865] _ARCH_PWR8 is not defined when using -mcpu=power8 Date: Thu, 02 May 2024 23:09:27 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 11.1.1 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: bergner at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D101865 --- Comment #27 from GCC Commits --- The releases/gcc-11 branch has been updated by Peter Bergner : https://gcc.gnu.org/g:f8f02fd0bfeeb733a044a120b394eeac48de318a commit r11-11413-gf8f02fd0bfeeb733a044a120b394eeac48de318a Author: Peter Bergner Date: Thu May 2 18:07:05 2024 -0500 rs6000: Add OPTION_MASK_POWER8 [PR101865] The bug in PR101865 is the _ARCH_PWR8 predefine macro is conditional up= on TARGET_DIRECT_MOVE, which can be false for some -mcpu=3Dpower8 compiles= if the -mno-altivec or -mno-vsx options are used. The solution here is to cre= ate a new OPTION_MASK_POWER8 mask that is true for -mcpu=3Dpower8, regardle= ss of Altivec or VSX enablement. Unfortunately, the only way to create an OPTION_MASK_* mask is to create a new option, which we have done here, but marked it as WarnRemoved sin= ce we do not want users using it. For stage1, we will look into how we can create ISA mask flags for use in the compiler without the need for expl= icit options. 2024-04-12 Will Schmidt Peter Bergner gcc/ PR target/101865 * config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Use OPTION_MASK_POWER8. * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add OPTION_MASK_POWER8. (ISA_2_7_MASKS_SERVER): Likewise. * config/rs6000/rs6000.c (rs6000_option_override_internal): Upd= ate comment. Use OPTION_MASK_POWER8 and TARGET_POWER8. * config/rs6000/rs6000.h (TARGET_SYNC_HI_QI): Use TARGET_POWER8. * config/rs6000/rs6000.md (define_attr "isa"): Add p8. (define_attr "enabled"): Handle it. (define_insn "prefetch"): Use TARGET_POWER8. * config/rs6000/rs6000.opt (mpower8-internal): New. gcc/testsuite/ PR target/101865 * gcc.target/powerpc/predefine-p7-novsx.c: New test. * gcc.target/powerpc/predefine-p8-noaltivec-novsx.c: New test. * gcc.target/powerpc/predefine-p8-noaltivec.c: New test. * gcc.target/powerpc/predefine-p8-novsx.c: New test. * gcc.target/powerpc/predefine-p8-pragma-vsx.c: New test. * gcc.target/powerpc/predefine-p9-novsx.c: New test. (cherry picked from commit aa57af93ba22865be747f926e4e5f219e7f8758a)=