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From: "jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug rtl-optimization/101885] [10/11/12 Regression] wrong code at
 -O3 on x86_64-linux-gnu
Date: Thu, 20 Jan 2022 17:27:39 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D101885

--- Comment #8 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
We have:
Trying 17 -> 130:
   17: {r124:QI=3Dr143:QI&r145:QI;clobber flags:CC;}
      REG_DEAD r145:QI
      REG_DEAD r143:QI
      REG_UNUSED flags:CC
  130: flags:CCZ=3Dcmp(r124:QI,0)
Successfully matched this instruction:
(parallel [
        (set (reg:CCZ 17 flags)
            (compare:CCZ (and:QI (reg:QI 143)
                    (reg:QI 145))
                (const_int 0 [0])))
        (set (reg:QI 124 [ _199 ])
            (and:QI (reg:QI 143)
                (reg:QI 145)))
    ])
That merged what we wanted, nice!

And then the wrong:
Trying 130 -> 132:
  130: {flags:CCZ=3Dcmp(r143:QI&r145:QI,0);r124:QI=3Dr143:QI&r145:QI;}
      REG_DEAD r143:QI
      REG_DEAD r145:QI
  132: r82:QI=3D{(flags:CCZ!=3D0)?r124:QI:r152:QI}
      REG_DEAD r152:QI
      REG_DEAD r124:QI
      REG_EQUAL {(flags:CCZ!=3D0)?r124:QI:0}
Failed to match this instruction:
(parallel [
        (set (reg:QI 82 [ b_lsm_flag.26 ])
            (and:QI (reg:QI 143)
                (reg:QI 145)))
        (set (reg:CCZ 17 flags)
            (compare:CCZ (and:QI (reg:QI 143)
                    (reg:QI 145))
                (const_int 0 [0])))
    ])
Failed to match this instruction:
(parallel [
        (set (reg:QI 82 [ b_lsm_flag.26 ])
            (and:QI (reg:QI 143)
                (reg:QI 145)))
        (set (reg:CCZ 17 flags)
            (compare:CCZ (and:QI (reg:QI 143)
                    (reg:QI 145))
                (const_int 0 [0])))
    ])
Successfully matched this instruction:
(set (reg:CCZ 17 flags)
    (compare:CCZ (and:QI (reg:QI 143)
            (reg:QI 145))
        (const_int 0 [0])))
Successfully matched this instruction:
(set (reg:QI 82 [ b_lsm_flag.26 ])
    (and:QI (reg:QI 143)
        (reg:QI 145)))
I guess it would be fine if (reg 17 flags) didn't have other users (in insn=
 135
in particular).

The failed match attempt
(parallel [
        (set (reg:QI 82 [ b_lsm_flag.26 ])
            (and:QI (reg:QI 143)
                (reg:QI 145)))
        (set (reg:CCZ 17 flags)
            (compare:CCZ (and:QI (reg:QI 143)
                    (reg:QI 145))
                (const_int 0 [0])))
    ])
actually looks almost good, except that it would need to try them in the ot=
her
order in the parallel.
I must say I forgot whether the flags first then operation ordering is now
canonical everywhere, or whether some backends want one and others another =
one.
But I vaguely remember there are various passes that only work with the
ordering x86 has.=