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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/101891] Adjust -fzero-call-used-regs to always use XOR
Date: Tue, 24 May 2022 15:55:00 +0000 [thread overview]
Message-ID: <bug-101891-4-gfWqHjp5r8@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-101891-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101891
--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-11 branch has been updated by Qing Zhao <qinzhao@gcc.gnu.org>:
https://gcc.gnu.org/g:c8d636cbe38b6a369528f58227c96b2b77b1fd3a
commit r11-10029-gc8d636cbe38b6a369528f58227c96b2b77b1fd3a
Author: Qing Zhao <qing.zhao@oracle.com>
Date: Tue May 24 15:54:06 2022 +0000
i386: Adjust -fzero-call-used-regs to always use XOR [PR101891]
Currently on i386, -fzero-call-used-regs uses a pattern of:
XOR regA,regA
MOV regA,regB
MOV regA,regC
...
RET
However, this introduces both a register ordering dependency (e.g. the CPU
cannot clear regB without clearing regA first), and while greatly reduces
available ROP gadgets, it does technically leave a set of "MOV" ROP gadgets
at the end of functions (e.g. "MOV regA,regC; RET").
This patch will switch to always use XOR on i386:
XOR regA,regA
XOR regB,regB
XOR regC,regC
...
RET
gcc/ChangeLog:
PR target/101891
* config/i386/i386.c (zero_call_used_regno_mode): use V2SImode
as a generic MMX mode instead of V4HImode.
(zero_all_mm_registers): Use SET to zero instead of MOV for
zeroing scratch registers.
(ix86_zero_call_used_regs): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/i386/zero-scratch-regs-1.c: Add -fno-stack-protector
-fno-PIC.
* gcc.target/i386/zero-scratch-regs-10.c: Adjust mov to xor.
* gcc.target/i386/zero-scratch-regs-13.c: Add -msse.
* gcc.target/i386/zero-scratch-regs-14.c: Adjust mov to xor.
* gcc.target/i386/zero-scratch-regs-15.c: Add -fno-stack-protector
-fno-PIC.
* gcc.target/i386/zero-scratch-regs-16.c: Likewise.
* gcc.target/i386/zero-scratch-regs-17.c: Likewise.
* gcc.target/i386/zero-scratch-regs-18.c: Add -fno-stack-protector
-fno-PIC, adjust mov to xor.
* gcc.target/i386/zero-scratch-regs-19.c: Add -fno-stack-protector
-fno-PIC.
* gcc.target/i386/zero-scratch-regs-2.c: Adjust mov to xor.
* gcc.target/i386/zero-scratch-regs-20.c: Add -msse.
* gcc.target/i386/zero-scratch-regs-21.c: Add -fno-stack-protector
-fno-PIC, Adjust mov to xor.
* gcc.target/i386/zero-scratch-regs-22.c: Adjust mov to xor.
* gcc.target/i386/zero-scratch-regs-23.c: Likewise.
* gcc.target/i386/zero-scratch-regs-26.c: Likewise.
* gcc.target/i386/zero-scratch-regs-27.c: Likewise.
* gcc.target/i386/zero-scratch-regs-28.c: Likewise.
* gcc.target/i386/zero-scratch-regs-3.c: Add -fno-stack-protector.
* gcc.target/i386/zero-scratch-regs-31.c: Adjust mov to xor.
* gcc.target/i386/zero-scratch-regs-4.c: Add -fno-stack-protector
-fno-PIC.
* gcc.target/i386/zero-scratch-regs-5.c: Adjust mov to xor.
* gcc.target/i386/zero-scratch-regs-6.c: Add -fno-stack-protector.
* gcc.target/i386/zero-scratch-regs-7.c: Likewise.
* gcc.target/i386/zero-scratch-regs-8.c: Adjust mov to xor.
* gcc.target/i386/zero-scratch-regs-9.c: Add -fno-stack-protector.
(cherry picked from commit 0b86943aca51175968e40bbb6f2662dfe3fbfe59)
next prev parent reply other threads:[~2022-05-24 15:55 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-12 19:47 [Bug middle-end/101891] New: " kees at outflux dot net
2021-08-12 20:08 ` [Bug target/101891] " pinskia at gcc dot gnu.org
2022-01-28 20:29 ` qinzhao at gcc dot gnu.org
2022-05-05 13:35 ` qinzhao at gcc dot gnu.org
2022-05-09 15:37 ` cvs-commit at gcc dot gnu.org
2022-05-09 15:43 ` qinzhao at gcc dot gnu.org
2022-05-24 15:04 ` cvs-commit at gcc dot gnu.org
2022-05-24 15:55 ` cvs-commit at gcc dot gnu.org [this message]
2022-05-24 15:55 ` qinzhao at gcc dot gnu.org
2022-05-24 16:42 ` arjan at linux dot intel.com
2022-05-24 18:47 ` qing.zhao at oracle dot com
2022-05-24 18:55 ` arjan at linux dot intel.com
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