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From: "joseph at codesourcery dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug libgcc/102017] libgcc ieee754-df.S for arm does not support exceptions
Date: Mon, 23 Aug 2021 19:51:15 +0000	[thread overview]
Message-ID: <bug-102017-4-ixPnCpd60M@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-102017-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102017

--- Comment #2 from joseph at codesourcery dot com <joseph at codesourcery dot com> ---
If you want to support exceptions and rounding modes for double precision 
on processors with hardware support for single-precision only 
floating-point arithmetic, I suggest using soft-fp instead of this 
Arm-specific code; lots of configurations use soft-fp integrated with 
hardware exceptions and rounding modes like that (e.g. for binary128 
TFmode arithmetic on architectures without hardware support for it but 
with hardware SFmode and DFmode support).

If you want to support exceptions, rounding modes or both on processors 
with no hardware floating-point, you have the complication of needing 
working TLS support from the runtime environment (if the floating-point 
code might ever be used in an environment with threads), because 
exceptions and rounding modes are thread-local (not global) state.

  parent reply	other threads:[~2021-08-23 19:51 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-23  8:33 [Bug libgcc/102017] New: " clyon at gcc dot gnu.org
2021-08-23 15:21 ` [Bug libgcc/102017] " rearnsha at gcc dot gnu.org
2021-08-23 19:51 ` joseph at codesourcery dot com [this message]
2021-09-24  8:59 ` clyon at gcc dot gnu.org
2022-09-22 16:44 ` torbjorn.svensson at foss dot st.com

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