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From: "rsandifo at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/102024] [12 Regression] zero width bitfields and ABIs
Date: Mon, 23 Aug 2021 16:17:21 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D102024

rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
     Ever confirmed|0                           |1
   Last reconfirmed|                            |2021-08-23

--- Comment #4 from rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.or=
g> ---
Thanks for raising this.  Just to summarise what I said on irc:

For aarch64 we'll have to decide between:

(a) keeping everything as it was for GCC 11, including the difference betwe=
en C
and C++
(b) keep the old C++ behaviour and make C match it
(c) keep the old C behaviour and make C++ match it (i.e. what happens on tr=
unk
now)

None of these are particularly appealing.  My understanding is that
(2) is what the psABI says, but we also have clang compatibility
to consider.

We'll need to discuss this internally a bit.  Obviously something
needs to be done in time for GCC 12, but due to other pressures,
I can't promise anything in time for end of stage 1.=