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From: "ktkachov at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/102066] aarch64: Suboptimal addressing modes for SVE
 LD1W, ST1W
Date: Wed, 25 Aug 2021 15:19:02 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D102066

--- Comment #2 from ktkachov at gcc dot gnu.org ---
(In reply to rsandifo@gcc.gnu.org from comment #1)
> > I guess the predicates and constraints in @aarch64_pred_mov<mode> in aa=
rch64-sve.md should allow for the scaled address modes
> They already allow them.  I'm guessing this is an ivopts problem,
> in that it doesn't realise it can promote the unsigned iterator
> to uint64_t for a svcntw() step.

ah indeed
#include <arm_sve.h>

void foo(int n, float *x, float *y) {
    for (uint64_t i=3D0; i<n; i+=3Dsvcntw()) {
        svfloat32_t val =3D svld1_f32(svptrue_b8(), &x[i]);
        svst1_f32(svptrue_b8(), &y[i], val);
    }
}

generates good code=