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From: "jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/102124] [11/12 Regression] -ftree-loop-vectorize Causing
 Data To Lose Sign Bit on AARCH64 Platform
Date: Mon, 30 Aug 2021 10:05:57 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D102124

--- Comment #5 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
I think the bug is in vect_recog_widen_op_pattern.
When we have half_type unsigned, for PLUS_EXPR, MULT_EXPR (and supposedly
LSHIFT_EXPR) it is ok that itype is twice the precision and same sign as
half_type, say
unsigned char uc1 =3D 0xfe, uc2 =3D 0xff;
int t1 =3D uc1, t2 =3D uc2;
t1 + t2 (or t1 * t2) wants to perform the widening operation and then
zero-extend to the result type.
But MINUS_EXPR seems to be special,
t1 - t2
is negative despite half_type being unsigned (and, even if type is unsigned,
such as for
unsigned u1 =3D uc1, u2 =3D uc2;
u1 - u2
wants sign-extension from unsigned short (aka itype) to unsigned int (aka t=
ype)
rather than zero-extension.=