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From: "jankowski938 at gmail dot com" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/102135] New: (ARM Cortex-M3 and newer) changing operation order may reduce number of instructions needed Date: Mon, 30 Aug 2021 20:24:13 +0000 [thread overview] Message-ID: <bug-102135-4@http.gcc.gnu.org/bugzilla/> (raw) https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102135 Bug ID: 102135 Summary: (ARM Cortex-M3 and newer) changing operation order may reduce number of instructions needed Product: gcc Version: 10.2.1 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: jankowski938 at gmail dot com Target Milestone: --- uint64_t foo64(const uint8_t *rData1) { uint64_t buffer; buffer = (((uint64_t)rData1[7]) << 56)|((uint64_t)(rData1[6]) << 48)|((uint64_t)(rData1[5]) << 40)|(((uint64_t)rData1[4]) << 32)| (((uint64_t)rData1[3]) << 24)|(((uint64_t)rData1[2]) << 16)|((uint64_t)(rData1[1]) << 8)|rData1[0]; ---- foo64: mov r3, r0 ldr r0, [r0] @ unaligned ldr r1, [r3, #4] @ unaligned bx lr Only 3 instructions are needed: ldr r1, [r0, #4] @ unaligned ldr r0, [r0] @ unaligned bx lr Options: -O3 -mthumb -mcpu=cortex-M4
next reply other threads:[~2021-08-30 20:24 UTC|newest] Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-30 20:24 jankowski938 at gmail dot com [this message] 2021-08-31 13:27 ` [Bug target/102135] " rearnsha at gcc dot gnu.org
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