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From: "wilson at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/102211] [12 regression] ICE introduced by r12-3277 Date: Wed, 08 Sep 2021 05:55:06 +0000 [thread overview] Message-ID: <bug-102211-4-yyZBmYYfBq@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-102211-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102211 Jim Wilson <wilson at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |wilson at gcc dot gnu.org --- Comment #4 from Jim Wilson <wilson at gcc dot gnu.org> --- Yes, moving SI/DI values to FP regs is OK. However, RISC-V requires that FP values in FP registers be stored NaN-boxed. So an SFmode value in a 64-bit FP reg has the upper 32-bits of all ones, and the lower 32-bits is the value. Thus if accessed as a 64-bit value, you get a NaN. The hardware may trap if you access a 32-bit value which is not properly NaN-boxed. Using qemu to check this may not be good enough, as last time I looked at qemu it wasn't handling NaN-boxing correctly, but this was over a year ago, so maybe it has been fixed since. I don't know. Anyways, this code sequence is OK foo: fmv.w.x fa0,a0 ret because we are moving a 32-bit SImode value to an FP reg and then treating it as SFmode, and the 32-bit move will properly NaN-box the SFmode value. This code sequence is not OK foo: fmv.d.x fa5,a0 fmul.s fa0,fa0,fa5 because we are moving a 64-bit DImode value to an FP reg and then treating it as SFmode, which is not OK because the value won't be NaN-boxed and may trap at run time. validate_subreg used to prevent the bad subreg from being created. I would think that TARGET_CAN_CHANGE_MODE_CLASS could help here, but it isn't being called inside general_operand when called from fwprop1 where the bad substitution happens. Because we have a pseudo-register, and it is only called for hard registers. I don't see a way to fix this as a backend change with current validate_subreg, other than by replacing register_operand with riscv_register_operand, and putting the subreg check I need inside riscv_register_operand. And likewise for any other affected predicate, like move_operand. This will be a big change, though a lot of it will be mechanical. As an optimization, we can continue to use register_operand in any pattern that can't use FP registers. As a middle end change, I need a new hook in general_operand to reject subregs that we can't support on RISC-V. Or maybe re-add the check I need to validate_subreg as a hook, so it can be conditionally enabled for RISC-V. We can allow (subreg:SF (reg:DI)) if it gets allocated to an integer register. It is only when it is allocated to an FP register that it can't work. I don't know offhand if that can be described. But disallowing the subreg always for RISC-V is simpler and also works.
next prev parent reply other threads:[~2021-09-08 5:55 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-06 2:53 [Bug target/102211] New: " crazylht at gmail dot com 2021-09-06 4:38 ` [Bug target/102211] " crazylht at gmail dot com 2021-09-06 4:50 ` crazylht at gmail dot com 2021-09-07 8:00 ` [Bug target/102211] [12 regression] " schwab@linux-m68k.org 2021-09-07 8:06 ` pinskia at gcc dot gnu.org 2021-09-08 5:55 ` wilson at gcc dot gnu.org [this message] 2021-09-09 23:49 ` Andrew Waterman 2021-09-08 5:55 ` wilson at gcc dot gnu.org 2021-09-09 5:31 ` wilson at gcc dot gnu.org 2021-09-09 23:30 ` segher at gcc dot gnu.org 2021-09-09 23:50 ` andrew at sifive dot com 2021-09-10 21:55 ` cvs-commit at gcc dot gnu.org 2021-09-13 17:35 ` wilson at gcc dot gnu.org 2021-09-13 17:43 ` wilson at gcc dot gnu.org 2022-01-17 13:33 ` rguenth at gcc dot gnu.org 2022-01-17 13:34 ` rguenth at gcc dot gnu.org
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