From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <gcc-bugzilla@gcc.gnu.org>
Received: by sourceware.org (Postfix, from userid 48)
 id 6FDB7385702B; Mon,  8 Aug 2022 13:38:34 +0000 (GMT)
DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6FDB7385702B
From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/102218] 128-bit atomic compare and exchange does not
 honor memory model on AArch64 and Arm
Date: Mon, 08 Aug 2022 13:38:34 +0000
X-Bugzilla-Reason: CC
X-Bugzilla-Type: changed
X-Bugzilla-Watch-Reason: None
X-Bugzilla-Product: gcc
X-Bugzilla-Component: target
X-Bugzilla-Version: 9.0
X-Bugzilla-Keywords: wrong-code
X-Bugzilla-Severity: normal
X-Bugzilla-Who: cvs-commit at gcc dot gnu.org
X-Bugzilla-Status: ASSIGNED
X-Bugzilla-Resolution: 
X-Bugzilla-Priority: P3
X-Bugzilla-Assigned-To: tnfchris at gcc dot gnu.org
X-Bugzilla-Target-Milestone: ---
X-Bugzilla-Flags: 
X-Bugzilla-Changed-Fields: 
Message-ID: <bug-102218-4-V1voc6pOEv@http.gcc.gnu.org/bugzilla/>
In-Reply-To: <bug-102218-4@http.gcc.gnu.org/bugzilla/>
References: <bug-102218-4@http.gcc.gnu.org/bugzilla/>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/
Auto-Submitted: auto-generated
MIME-Version: 1.0
X-BeenThere: gcc-bugs@gcc.gnu.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: Gcc-bugs mailing list <gcc-bugs.gcc.gnu.org>
List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-bugs>,
 <mailto:gcc-bugs-request@gcc.gnu.org?subject=unsubscribe>
List-Archive: <https://gcc.gnu.org/pipermail/gcc-bugs/>
List-Post: <mailto:gcc-bugs@gcc.gnu.org>
List-Help: <mailto:gcc-bugs-request@gcc.gnu.org?subject=help>
List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-bugs>,
 <mailto:gcc-bugs-request@gcc.gnu.org?subject=subscribe>
X-List-Received-Date: Mon, 08 Aug 2022 13:38:34 -0000

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D102218

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Tamar Christina <tnfchris@gcc.gnu.org=
>:

https://gcc.gnu.org/g:5471f55f001af412e1125b04972ebaab9d4f7337

commit r13-1989-g5471f55f001af412e1125b04972ebaab9d4f7337
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Mon Aug 8 14:37:42 2022 +0100

    AArch32: Fix 128-bit sequential consistency atomic operations.

    Similar to AArch64 the Arm implementation of 128-bit atomics is broken.

    For 128-bit atomics we rely on pthread barriers to correct guard the
address
    in the pointer to get correct memory ordering.  However for 128-bit ato=
mics
the
    address under the lock is different from the original pointer.

    This means that one of the values under the atomic operation is not
protected
    properly and so we fail during when the user has requested sequential
    consistency as there's no barrier to enforce this requirement.

    As such users have resorted to adding an

    #ifdef GCC
    <emit barrier>
    #endif

    around the use of these atomics.

    This corrects the issue by issuing a barrier only when __ATOMIC_SEQ_CST=
 was
    requested.  I have hand verified that the barriers are inserted
    for atomic seq cst.

    libatomic/ChangeLog:

            PR target/102218
            * config/arm/host-config.h (pre_seq_barrier, post_seq_barrier,
            pre_post_seq_barrier): Require barrier on __ATOMIC_SEQ_CST.=