From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id F413C3858D34; Sat, 18 Sep 2021 00:03:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F413C3858D34 From: "gabravier at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug tree-optimization/102391] Failure to optimize adjacent 8-bit loads into a single bigger load Date: Sat, 18 Sep 2021 00:03:04 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: tree-optimization X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: gabravier at gmail dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: short_desc Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 18 Sep 2021 00:03:05 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D102391 Gabriel Ravier changed: What |Removed |Added ---------------------------------------------------------------------------- Summary|Failure to optimize 2 8-bit |Failure to optimize |loads into a single 16-bit |adjacent 8-bit loads into a |load |single bigger load --- Comment #1 from Gabriel Ravier --- Note: this also equivalently works on bigger sizes: uint32_t HeaderReadU32LE(int offset, uint8_t *RomHeader) { return RomHeader[offset] | (RomHeader[offset + 1] << 8) | (RomHeader[offset + 2] << 16) | (RomHeader[offset + 3] << 24); } On AMD64, GCC outputs this: HeaderReadU32LE: movsx rdi, edi movzx eax, BYTE PTR [rsi+1+rdi] movzx edx, BYTE PTR [rsi+2+rdi] sal eax, 8 sal edx, 16 or eax, edx movzx edx, BYTE PTR [rsi+rdi] or eax, edx movzx edx, BYTE PTR [rsi+3+rdi] sal edx, 24 or eax, edx ret LLVM manages this: HeaderReadU32LE: movsxd rax, edi mov eax, dword ptr [rsi + rax] ret=