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From: "rguenth at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/102583] [x86] Failure to optimize 32-byte integer vector
 conversion to 16-byte float vector properly when converting upper
 part with -mavx2
Date: Mon, 04 Oct 2021 07:53:15 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D102583

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2021-10-04
     Ever confirmed|0                           |1

--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
We're lacking stripping of a load that's only used partially I guess.=20
forwprop1
generates

  _1 =3D *srcp_11(D);
  _2 =3D BIT_FIELD_REF <_1, 32, 128>;
  _3 =3D (float) _2;
  _4 =3D BIT_FIELD_REF <_1, 32, 160>;
  _5 =3D (float) _4;
  _6 =3D BIT_FIELD_REF <_1, 32, 192>;
  _7 =3D (float) _6;
  _8 =3D BIT_FIELD_REF <_1, 32, 224>;
  _9 =3D (float) _8;
  _12 =3D VEC_PERM_EXPR <_1, _1, { 4, 5, 6, 7, 4, 5, 6, 7 }>;
  _15 =3D BIT_FIELD_REF <_12, 128, 0>;
  _16 =3D (vector(4) float) _15;

and the second forwprop then sees

  _1 =3D *srcp_3(D);
  _4 =3D VEC_PERM_EXPR <_1, _1, { 4, 5, 6, 7, 4, 5, 6, 7 }>;
  _5 =3D BIT_FIELD_REF <_4, 128, 0>;
  _6 =3D (vector(4) float) _5;

in a single-use chain we probably want to try swapping the
BIT_FIELD_REF and the VEC_PERM_EXPR so that we expose the
BIT_FIELD_REF directly to the load which we'd already handle.=